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From: cvs at opencores.org<cvs@o...>
Date: Fri Mar 14 16:52:44 CET 2008
Subject: [cvs-checkins] MODIFIED: System09 ...
Date: 00/08/03 14:16:52

Modified: System09/rtl/System09_Digilent_3S200
System09_Digilent_3S200.ise
System09_Digilent_3S200.ucf
System09_Digilent_3S200.vhd
Log:
Updated software - XSA-3S1000 now runs FLEX on an IDE drive or CF card.


Revision Changes Path
1.2 System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.ise

http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.ise?rev=1.2&content-type=text/x-cvsweb-markup

<<Binary file>>


1.2 System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.ucf

http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.ucf.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: System09_Digilent_3S200.ucf
===================================================================
RCS file: /cvsroot/dilbert57/System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.ucf,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- System09_Digilent_3S200.ucf 9 Dec 2007 16:06:01 -0000 1.1
+++ System09_Digilent_3S200.ucf 14 Mar 2008 15:52:44 -0000 1.2
@@ -1,11 +1,11 @@
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
-NET "SysClk" LOC = "T9" ;
+NET "sys_clk" LOC = "T9" ;
#
# PUSH BUTTONS
#
-NET "Reset_sw" LOC = "L14" ;
+NET "rst_sw" LOC = "L14" ;
NET "nmi_sw" LOC = "L13" ;
#
# LEDs
@@ -130,79 +130,10 @@
NET "ram2_data<14>" LOC = "M1" ;
NET "ram2_data<15>" LOC = "N1" ;
#
-# Timing Groups
-#
-INST "ram_oen" TNM = "gram_rw";
-INST "ram_wen" TNM = "gram_rw";
-INST "ram_addr<0>" TNM = "gram_addr";
-INST "ram_addr<1>" TNM = "gram_addr";
-INST "ram_addr<2>" TNM = "gram_addr";
-INST "ram_addr<3>" TNM = "gram_addr";
-INST "ram_addr<4>" TNM = "gram_addr";
-INST "ram_addr<5>" TNM = "gram_addr";
-INST "ram_addr<6>" TNM = "gram_addr";
-INST "ram_addr<7>" TNM = "gram_addr";
-INST "ram_addr<8>" TNM = "gram_addr";
-INST "ram_addr<9>" TNM = "gram_addr";
-INST "ram_addr<10>" TNM = "gram_addr";
-INST "ram_addr<11>" TNM = "gram_addr";
-INST "ram_addr<12>" TNM = "gram_addr";
-INST "ram_addr<13>" TNM = "gram_addr";
-INST "ram_addr<14>" TNM = "gram_addr";
-INST "ram_addr<15>" TNM = "gram_addr";
-INST "ram_addr<16>" TNM = "gram_addr";
-INST "ram_addr<17>" TNM = "gram_addr";
-#
-INST "ram1_cen" TNM = "gram_cs";
-INST "ram1_lbn" TNM = "gram_ds";
-INST "ram1_ubn" TNM = "gram_ds";
-INST "ram1_data<0>" TNM = "gram_data";
-INST "ram1_data<1>" TNM = "gram_data";
-INST "ram1_data<2>" TNM = "gram_data";
-INST "ram1_data<3>" TNM = "gram_data";
-INST "ram1_data<4>" TNM = "gram_data";
-INST "ram1_data<5>" TNM = "gram_data";
-INST "ram1_data<6>" TNM = "gram_data";
-INST "ram1_data<7>" TNM = "gram_data";
-INST "ram1_data<8>" TNM = "gram_data";
-INST "ram1_data<9>" TNM = "gram_data";
-INST "ram1_data<10>" TNM = "gram_data";
-INST "ram1_data<11>" TNM = "gram_data";
-INST "ram1_data<12>" TNM = "gram_data";
-INST "ram1_data<13>" TNM = "gram_data";
-INST "ram1_data<14>" TNM = "gram_data";
-INST "ram1_data<15>" TNM = "gram_data";
-#
-INST "ram2_cen" TNM = "gram_cs";
-INST "ram2_lbn" TNM = "gram_ds";
-INST "ram2_ubn" TNM = "gram_ds";
-INST "ram2_data<0>" TNM = "gram_data";
-INST "ram2_data<1>" TNM = "gram_data";
-INST "ram2_data<2>" TNM = "gram_data";
-INST "ram2_data<3>" TNM = "gram_data";
-INST "ram2_data<4>" TNM = "gram_data";
-INST "ram2_data<5>" TNM = "gram_data";
-INST "ram2_data<6>" TNM = "gram_data"; -INST "ram2_data<7>" TNM = "gram_data"; -INST "ram2_data<8>" TNM = "gram_data"; -INST "ram2_data<9>" TNM = "gram_data"; -INST "ram2_data<10>" TNM = "gram_data"; -INST "ram2_data<11>" TNM = "gram_data"; -INST "ram2_data<12>" TNM = "gram_data"; -INST "ram2_data<13>" TNM = "gram_data"; -INST "ram2_data<14>" TNM = "gram_data"; -INST "ram2_data<15>" TNM = "gram_data"; -# # Timing Constraints # -NET "sysclk" TNM_NET = "sysclk"; -TIMESPEC "TS_sysclk" = PERIOD "sysclk" 20 ns LOW 50 %; -TIMEGRP "gram_cs" OFFSET = OUT 20 ns AFTER "sysclk"; -TIMEGRP "gram_ds" OFFSET = OUT 20 ns AFTER "sysclk"; -TIMEGRP "gram_rw" OFFSET = OUT 20 ns AFTER "sysclk"; -TIMEGRP "gram_addr" OFFSET = OUT 20 ns AFTER "sysclk"; -TIMEGRP "gram_data" OFFSET = OUT 20 ns AFTER "sysclk"; -TIMEGRP "gram_data" OFFSET = IN 10 ns BEFORE "sysclk"; +NET "sys_clk" TNM_NET = "sys_clk"; +TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 20 ns LOW 50 %; #PACE: Start of PACE Area Constraints 1.2 System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.vhd http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: System09_Digilent_3S200.vhd =================================================================== RCS file: /cvsroot/dilbert57/System09/rtl/System09_Digilent_3S200/System09_Digilent_3S200.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- System09_Digilent_3S200.vhd 9 Dec 2007 16:06:01 -0000 1.1 +++ System09_Digilent_3S200.vhd 14 Mar 2008 15:52:44 -0000 1.2 @@ -49,7 +49,7 @@ -- Runs SBUG -- -- Version 1.0- 6 Sep 2003 - John Kent --- Inverted SysClk +-- Inverted sys_clk -- Initial release to Open Cores -- -- Version 1.1 - 17 Jan 2004 - John Kent @@ -84,10 +84,14 @@ -- Added LED output register -- Changed address decoding to 4K Blocks -- --- Vesrion 2.3 - 1 June 2007 - John Kent +-- Version 2.3 - 1 June 2007 - John Kent -- Updated VDU & ACIA -- Changed decoding for Sys09Bug -- +-- Version 2.4 - 31 January 2008 - John Kent +-- ACIA does not appear to work. +-- Made RAM OE and WE strobes synchonous to sys_clk +-- --===========================================================================-- library ieee; use ieee.std_logic_1164.all; @@ -97,8 +101,8 @@ entity My_System09 is port( - SysClk : in Std_Logic; -- System Clock input - Reset_sw : in Std_logic; -- Master Reset input (active low) + sys_clk : in Std_Logic; -- System Clock input + rst_sw : in Std_logic; -- Master Reset input (active high) nmi_sw : in Std_logic; -- Memory Interface signals @@ -120,7 +124,7 @@ ps2c : inout Std_logic; ps2d : inout Std_Logic; - -- Uart Interface + -- ACIA Interface rxd : in Std_Logic; txd : out Std_Logic; @@ -167,14 +171,16 @@ signal flex_cs : Std_logic; signal flex_data_out : Std_Logic_Vector(7 downto 0); - -- UART Interface signals + -- ACIA Interface signals signal acia_clk : std_logic; signal acia_data_out : Std_Logic_Vector(7 downto 0); signal acia_cs : Std_Logic; signal acia_irq : Std_Logic; - signal DCD_n : Std_Logic; - signal RTS_n : Std_Logic; - signal CTS_n : Std_Logic; + signal acia_rxd : Std_Logic; + signal acia_txd : Std_Logic; + signal acia_dcd_n : Std_Logic; +-- signal acia_rts_n : Std_Logic; + signal acia_cts_n : Std_Logic; -- keyboard port signal keyboard_data_out : std_logic_vector(7 downto 0); @@ -306,7 +312,7 @@ ----------------------------------------------------------------- -- --- Open Cores Mini UART +-- 6850 ACIA -- ----------------------------------------------------------------- @@ -314,7 +320,7 @@ port ( clk : in Std_Logic; -- System Clock rst : in Std_Logic; -- Reset input (active high) - cs : in Std_Logic; -- miniUART Chip Select + cs : in Std_Logic; -- ACIA Chip Select rw : in Std_Logic; -- Read / Not Write irq : out Std_Logic; -- Interrupt Addr : in Std_Logic; -- Register Select @@ -501,11 +507,11 @@ DataOut => acia_data_out, RxC => acia_clk, TxC => acia_clk, - RxD => rxd, - TxD => txd, - DCD_n => dcd_n, - CTS_n => cts_n, - RTS_n => rts_n + RxD => acia_rxd, + TxD => acia_txd, + DCD_n => acia_dcd_n, + CTS_n => acia_cts_n, + RTS_n => open ); @@ -520,7 +526,7 @@ ACIA_Clock_Frequency => ACIA_Clock_Frequency ) port map( - clk => SysClk, + clk => sys_clk, acia_clk => acia_clk ); @@ -623,9 +629,9 @@ -- 25MHz pixel clock -- 25MHz CPU clock -- -sys09_clock : process( SysClk, clk_count ) +sys09_clock : process( sys_clk, clk_count ) begin - if SysClk'event and SysClk='0' then + if sys_clk'event and sys_clk='1' then clk_count <= not clk_count; end if; end process; @@ -636,8 +642,7 @@ -- ---------------------------------------------------------------------- -mem_decode: process( cpu_clk, Reset_sw, - cpu_addr, cpu_rw, cpu_vma, +mem_decode: process( cpu_addr, cpu_rw, cpu_vma, dat_cs, dat_addr, rom_data_out, acia_data_out, @@ -649,10 +654,9 @@ ram_data_out ) begin - if cpu_addr( 15 downto 8 ) = "11111111" then - cpu_data_in <= rom_data_out; - dat_cs <= cpu_vma; -- write DAT - rom_cs <= cpu_vma; -- read ROM + cpu_data_in <= (others=>'0'); + dat_cs <= '0'; + rom_cs <= '0'; acia_cs <= '0'; keyboard_cs <= '0'; vdu_cs <= '0'; @@ -660,40 +664,44 @@ leds_cs <= '0'; flex_cs <= '0'; ram_cs <= '0'; - else - case dat_addr(3 downto 0) is +-- timer_cs <= '0'; +-- trap_cs <= '0'; +-- pb_cs <= '0'; +-- ide_cs <= '0'; +-- ether_cs <= '0'; +-- slot1_cs <= '0'; +-- slot2_cs <= '0'; + + if cpu_addr( 15 downto 8 ) = "11111111" then + cpu_data_in <= rom_data_out; + dat_cs <= cpu_vma; -- write DAT + rom_cs <= cpu_vma; -- read ROM + -- + -- Sys09Bug Monitor ROM $F000 - $FFFF + -- + elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF -- -- Monitor ROM $F000 - $FFFF -- - when "1111" => -- $XF000 - $XFFFF cpu_data_in <= rom_data_out; - dat_cs <= '0'; -- write DAT rom_cs <= cpu_vma; -- read ROM - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - seg_cs <= '0'; - leds_cs <= '0'; - flex_cs <= '0'; - ram_cs <= '0'; -- -- IO Devices $E000 - $EFFF -- - when "1110" => -- $XE000 - $XEFFF - dat_cs <= '0'; - rom_cs <= '0'; + elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF + case cpu_addr(11 downto 8) is + -- + -- SWTPC peripherals from $E000 to $E0FF + -- + when "0000" => case cpu_addr(7 downto 4) is -- - -- UART / ACIA ($E000 - $E00F) + -- ACIA ($E000 - $E00F) -- when "0000" => cpu_data_in <= acia_data_out; acia_cs <= cpu_vma; - keyboard_cs <= '0'; - vdu_cs <= '0'; - seg_cs <= '0'; - leds_cs <= '0'; -- -- Reserved - FD1771 FDC ($E010 - $E01F) (SWTPC) @@ -704,25 +712,17 @@ -- when "0010" => cpu_data_in <= keyboard_data_out; - acia_cs <= '0'; keyboard_cs <= cpu_vma; - vdu_cs <= '0'; - seg_cs <= '0'; - leds_cs <= '0'; -- -- VDU port ($E030 - $E03F) -- when "0011" => cpu_data_in <= vdu_data_out; - acia_cs <= '0'; - keyboard_cs <= '0'; vdu_cs <= cpu_vma; - seg_cs <= '0'; - leds_cs <= '0'; -- - -- Reserved - Compact Flash ($E040 - $E04F) (B5-X300) + -- Reserved - SWTPc MP-T ($E040 - $E04F) -- -- @@ -751,10 +751,6 @@ -- when "1010" => cpu_data_in <= leds_data_out; - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - seg_cs <= '0'; leds_cs <= cpu_vma; -- @@ -762,58 +758,66 @@ -- when "1011" => cpu_data_in <= seg_data_out; - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; seg_cs <= cpu_vma; - leds_cs <= '0'; when others => -- $EXC0 to $EXFF - cpu_data_in <= "00000000"; - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - seg_cs <= '0'; - leds_cs <= '0'; + null; + end case; + -- + -- XST-3.0 Peripheral Bus goes here + -- $E100 to $E1FF + -- Four devices + -- IDE, Ethernet, Slot1, Slot2 + -- +-- when "0001" => +-- cpu_data_in <= pb_data_out; +-- pb_cs <= cpu_vma; +-- case cpu_addr(7 downto 6) is + -- + -- IDE Interface $E100 to $E13F + -- +-- when "00" => +-- ide_cs <= cpu_vma; + -- + -- Ethernet Interface $E140 to $E17F + -- +-- when "01" => +-- ether_cs <= cpu_vma; + -- + -- Slot 1 Interface $E180 to $E1BF + -- +-- when "10" => +-- slot1_cs <= cpu_vma; + -- + -- Slot 2 Interface $E1C0 to $E1FF + -- +-- when "11" => +-- slot2_cs <= cpu_vma; + -- + -- Nothing else + -- +-- when others => +-- null; +-- end case; + -- + -- $E200 to $EFFF reserved for future use + -- + when others => + null; end case; - flex_cs <= '0'; - ram_cs <= '0'; -- -- FLEX RAM $0C000 - $0DFFF -- - when "1100" | "1101" => -- $0C000 - $0DFFF - if dat_addr(7 downto 4) = "0000" then + elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF cpu_data_in <= flex_data_out; flex_cs <= cpu_vma; - ram_cs <= '0'; - else - cpu_data_in <= ram_data_out; - flex_cs <= '0'; - ram_cs <= cpu_vma; - end if; - dat_cs <= '0'; - rom_cs <= '0'; - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - seg_cs <= '0'; - leds_cs <= '0'; -- -- Everything else is RAM -- - when others => + else cpu_data_in <= ram_data_out; - rom_cs <= '0'; ram_cs <= cpu_vma; - dat_cs <= '0'; - acia_cs <= '0'; - keyboard_cs <= '0'; - vdu_cs <= '0'; - seg_cs <= '0'; - leds_cs <= '0'; - flex_cs <= '0'; - end case; end if; end process; @@ -822,15 +826,32 @@ -- 1M byte SRAM Control -- Processes to read and write memory based on bus signals -- -ram_process: process( cpu_clk, +ram_process: process( cpu_reset, sys_clk, cpu_addr, cpu_rw, cpu_vma, cpu_data_out, dat_addr, ram_cs, ram1_ce, ram1_ub, ram1_lb, ram1_data, ram2_ce, ram2_ub, ram2_lb, ram2_data, ram_we, ram_oe ) begin - ram_we <= (not cpu_rw) and cpu_clk; - ram_oe <= cpu_rw and cpu_clk; + -- + -- ram_hold signal helps + -- + if( cpu_reset = '1' ) then + ram_we <= '0'; + ram_oe <= '0'; + -- + -- Clock Hold on rising edge + -- + elsif( sys_clk'event and sys_clk='1' ) then + if (ram_cs = '1') and (ram_we = '0') and (ram_oe = '0') then + ram_we <= not cpu_rw; + ram_oe <= cpu_rw; + else + ram_we <= '0'; + ram_oe <= '0'; + end if; + end if; + ram_wen <= not ram_we; ram_oen <= not ram_oe; @@ -905,21 +926,31 @@ -- -- Interrupts and other bus control signals -- -interrupts : process( Reset_sw, +interrupts : process( rst_sw, acia_irq, keyboard_irq, nmi_sw ) begin - cpu_reset <= Reset_sw; -- CPU reset is active high + if sys_clk'event and sys_clk = '1' then + cpu_reset <= rst_sw; -- CPU reset is active high + end if; cpu_firq <= keyboard_irq; cpu_nmi <= nmi_sw; cpu_irq <= acia_irq; cpu_halt <= '0'; cpu_hold <= '0'; +end process; - DCD_n <= '0'; - CTS_n <= '0'; +-- +-- ACIA pin assignments +-- +acia_assignments : process( rxd, acia_txd ) +begin + acia_dcd_n <= '0'; + acia_cts_n <= '0'; + acia_rxd <= rxd; + txd <= acia_txd; end process;