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Message
From: cvs at opencores.org<cvs@o...>
Date: Fri Mar 14 16:52:43 CET 2008
Subject: [cvs-checkins] MODIFIED: System09 ...
Date: 00/08/03 14:16:52 Modified: System09/rtl/System09_BurchED_B5-X300
System09_BurchED_B5-X300.ucf
System09_BurchED_B5-X300.vhd
Log:
Updated software - XSA-3S1000 now runs FLEX on an IDE drive or CF card.
Revision Changes Path
1.2 System09/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.ucf
http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.ucf.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: System09_BurchED_B5-X300.ucf
===================================================================
RCS file: /cvsroot/dilbert57/System09/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.ucf,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- System09_BurchED_B5-X300.ucf 9 Dec 2007 16:06:00 -0000 1.1
+++ System09_BurchED_B5-X300.ucf 14 Mar 2008 15:52:43 -0000 1.2
@@ -34,7 +34,7 @@
NET "cf_d<0>" LOC = "P36" ; #J2-9
NET "cf_d<1>" LOC = "P40" ; #J2-10
NET "cf_d<2>" LOC = "P41" ; #J2-11
-NET "cf_cs16_n" LOC = "P42" ; #J2-12
+#NET "cf_cs16_n" LOC = "P42" ; #J2-12
NET "cf_d<10>" LOC = "P43" ; #J2-13
NET "cf_d<9>" LOC = "P44" ; #J2-14
NET "cf_d<8>" LOC = "P45" ; #J2-15
1.2 System09/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.vhd
http://www.opencores.org/cvsweb.shtml/System09/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: System09_BurchED_B5-X300.vhd
===================================================================
RCS file: /cvsroot/dilbert57/System09/rtl/System09_BurchED_B5-X300/System09_BurchED_B5-X300.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- System09_BurchED_B5-X300.vhd 9 Dec 2007 16:06:00 -0000 1.1
+++ System09_BurchED_B5-X300.vhd 14 Mar 2008 15:52:43 -0000 1.2
@@ -165,10 +165,8 @@
cf_cs1_n : out std_logic;
cf_rd_n : out std_logic;
cf_wr_n : out std_logic;
- cf_cs16_n : out std_logic;
cf_a : out std_logic_vector(2 downto 0);
cf_d : inout std_logic_vector(15 downto 0);
--- cf_d : inout std_logic_vector(7 downto 0);
-- Parallel I/O port
porta : inout std_logic_vector(7 downto 0);
@@ -982,7 +980,6 @@
cf_rst_n <= Reset_n;
cf_cs0_n <= not( cf_cs ) or cpu_addr(3);
cf_cs1_n <= not( cf_cs and cpu_addr(3));
- cf_cs16_n <= '1';
cf_wr <= cf_cs and (not cpu_rw);
cf_rd <= cf_cs and cpu_rw;
cf_wr_n <= not cf_wr;
@@ -990,11 +987,12 @@
cf_a <= cpu_addr(2 downto 0);
if cf_wr = '1' then
cf_d(7 downto 0) <= cpu_data_out;
+ cf_d(15 downto 8) <= (others => '0');
else
- cf_d(7 downto 0) <= "ZZZZZZZZ";
+ cf_d(7 downto 0) <= (others => 'Z');
+ cf_d(15 downto 8) <= (others => 'Z');
end if;
cf_data_out <= cf_d(7 downto 0);
- cf_d(15 downto 8) <= "ZZZZZZZZ";
end process;
--
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