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From: cvs at opencores.org<cvs@o...>
Date: Tue Feb 26 11:56:54 CET 2008
Subject: [cvs-checkins] MODIFIED: usb_dongle_fpga ...
Date: 00/08/02 26:11:56

Modified: usb_dongle_fpga/beh lpc_byte_test.vhd
Log:
Fix'ed TAR cycle second part this is not critical update


Revision Changes Path
1.2 usb_dongle_fpga/beh/lpc_byte_test.vhd

http://www.opencores.org/cvsweb.shtml/usb_dongle_fpga/beh/lpc_byte_test.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: lpc_byte_test.vhd
===================================================================
RCS file: /cvsroot/nuubik/usb_dongle_fpga/beh/lpc_byte_test.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- lpc_byte_test.vhd 7 Dec 2006 10:46:36 -0000 1.1
+++ lpc_byte_test.vhd 26 Feb 2008 10:56:54 -0000 1.2
@@ -62,6 +62,8 @@
PORT(
lreset_n : IN std_logic;
lclk : IN std_logic;
+ lena_mem_r : in std_logic; --enable lpc regular memory read cycles also (default is only LPC firmware read)
+ lena_reads : in std_logic; --enable read capabilities
lad_i : IN std_logic_vector(3 downto 0);
lframe_n : IN std_logic;
lpc_data_i : IN std_logic_vector(7 downto 0);
@@ -78,6 +80,10 @@
--Inputs
SIGNAL lreset_n : std_logic := '0';
SIGNAL lclk : std_logic := '0';
+
+ SIGNAL lena_mem_r : std_logic:='1'; --enable lpc regular memory read cycles also (default is only LPC firmware read)
+ SIGNAL lena_reads : std_logic:='1'; --enable read capabilities
+
SIGNAL lframe_n : std_logic := '1';
SIGNAL lpc_ack : std_logic := '0';
SIGNAL lad_i : std_logic_vector(3 downto 0) := (others=>'0');
@@ -97,6 +103,8 @@
uut: lpc_iow PORT MAP(
lreset_n => lreset_n,
lclk => lclk,
+ lena_mem_r=> lena_mem_r,
+ lena_reads => lena_reads,
lad_i => lad_i,
lad_o => lad_o,
lad_oe => lad_oe,
@@ -165,13 +173,18 @@
lad_i <=x"F"; --TAR 1
wait until lclk='0'; --cycle 10
wait until lclk='1';
- if lad_o=x"F" and lad_oe='1' then --TAR 2
+ if lad_oe='0' then --TAR 2
else
report "LPC error found on TAR cycle no 0xF on lad_o";
lframe_n <='0';
end if;
wait until lclk='0'; --cycle 11
wait until lclk='1';
+ wait until lad_o=x"6";
+ while(lad_o=x"6") loop
+ wait until lclk='0'; --cycle 11
+ wait until lclk='1';
+ end loop;
if (lad_o=x"0") and lad_oe='1' then --SYNC
else
report "LPC error found on SYNC cycle no 0x0 on lad_o";