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From: cvs at opencores.org<cvs@o...>
Date: Tue Feb 26 10:04:23 CET 2008
Subject: [cvs-checkins] MODIFIED: usb_dongle_fpga ...
Date: 00/08/02 26:10:04

Modified: usb_dongle_fpga/src/lpc_proto lpc_byte.vhd
Log:
Fix'ed cycle type init code copy/pase mistake


Revision Changes Path
1.4 usb_dongle_fpga/src/lpc_proto/lpc_byte.vhd

http://www.opencores.org/cvsweb.shtml/usb_dongle_fpga/src/lpc_proto/lpc_byte.vhd.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: lpc_byte.vhd
===================================================================
RCS file: /cvsroot/nuubik/usb_dongle_fpga/src/lpc_proto/lpc_byte.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- lpc_byte.vhd 25 Feb 2008 09:45:50 -0000 1.3
+++ lpc_byte.vhd 26 Feb 2008 09:04:23 -0000 1.4
@@ -109,7 +109,7 @@
lpc_val <='0';
lpc_wr <='0';
r_lad <= (others=>'0');
- cycle_type <= (others=>'0');
+ cycle_type <= LPC_IO_W; --initial value
r_addr <= (others=>'0');
r_cnt <= (others=>'0');
elsif lclk'event and lclk = '1' then -- rising clock edge