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From: cvs at opencores.org<cvs@o...>
Date: Mon Feb 25 10:45:51 CET 2008
Subject: [cvs-checkins] MODIFIED: usb_dongle_fpga ...
Date: 00/08/02 25:10:45

Modified: usb_dongle_fpga/src/lpc_proto lpc_byte.vhd
Log:
Fixed in reset init of some trigers (this should not have generated extra hardware in FPGA but just to be on the safe side)


Revision Changes Path
1.3 usb_dongle_fpga/src/lpc_proto/lpc_byte.vhd

http://www.opencores.org/cvsweb.shtml/usb_dongle_fpga/src/lpc_proto/lpc_byte.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: lpc_byte.vhd
===================================================================
RCS file: /cvsroot/nuubik/usb_dongle_fpga/src/lpc_proto/lpc_byte.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- lpc_byte.vhd 25 Feb 2008 09:13:58 -0000 1.2
+++ lpc_byte.vhd 25 Feb 2008 09:45:50 -0000 1.3
@@ -107,7 +107,11 @@
data_valid <='1';
lad_rising_o<="0000";
lpc_val <='0';
+ lpc_wr <='0';
+ r_lad <= (others=>'0');
+ cycle_type <= (others=>'0');
r_addr <= (others=>'0');
+ r_cnt <= (others=>'0');
elsif lclk'event and lclk = '1' then -- rising clock edge
case CS is
when RESETs => ----------------------------------------------------------