Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Mon Jan 21 02:02:26 CET 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/01 21:02:02

Modified: aemb/rtl/verilog aeMB_ibuf.v
Log:
Patch interrupt bug.




Revision Changes Path
1.10 aemb/rtl/verilog/aeMB_ibuf.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_ibuf.v.diff?r1=1.9&r2=1.10

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_ibuf.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_ibuf.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- aeMB_ibuf.v 19 Jan 2008 16:01:22 -0000 1.9
+++ aeMB_ibuf.v 21 Jan 2008 01:02:26 -0000 1.10
@@ -1,4 +1,4 @@
-/* $Id: aeMB_ibuf.v,v 1.9 2008/01/19 16:01:22 sybreon Exp $
+/* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $
**
** AEMB INSTRUCTION BUFFER
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -89,9 +89,14 @@
rDINT <= 2'h0;
rFINT <= 1'h0;
// End of automatics
- end else if (rMSR_IE) begin
- rDINT <= #1 {rDINT[0], sys_int_i};
- rFINT <= #1 (wIREG == wINTOP) ? 1'b0 : (rFINT | wSHOT);
+ end else begin
+ if (rMSR_IE)
+ rDINT <= #1
+ {rDINT[0], sys_int_i};
+
+ rFINT <= #1
+ //(wIREG == wINTOP) ? 1'b0 :
+ (rFINT | wSHOT) & rMSR_IE;
end

wire fIMM = (rOPC == 6'o54);
@@ -151,6 +156,9 @@

/*
$Log: aeMB_ibuf.v,v $
+ Revision 1.10 2008/01/21 01:02:26 sybreon
+ Patch interrupt bug.
+
Revision 1.9 2008/01/19 16:01:22 sybreon
Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)