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From: cvs at opencores.org<cvs@o...>
Date: Sat Jan 19 17:01:22 CET 2008
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/08/01 19:17:01

Modified: aemb/rtl/verilog aeMB_edk32.v aeMB_ibuf.v
Log:
Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)


Revision Changes Path
1.14 aemb/rtl/verilog/aeMB_edk32.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_edk32.v.diff?r1=1.13&r2=1.14

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_edk32.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_edk32.v,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -b -r1.13 -r1.14
--- aeMB_edk32.v 25 Dec 2007 22:15:09 -0000 1.13
+++ aeMB_edk32.v 19 Jan 2008 16:01:22 -0000 1.14
@@ -1,4 +1,4 @@
-/* $Id: aeMB_edk32.v,v 1.13 2007/12/25 22:15:09 sybreon Exp $
+/* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $
**
** AEMB EDK 3.2 Compatible Core
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -32,7 +32,7 @@
parameter DW = 32; /// Data bus address width

// Optional functions
- parameter MUL = 1; // Multiplier
+ parameter MUL = 0; // Multiplier
parameter BSF = 1; // Barrel Shifter

/*AUTOOUTPUT*/
@@ -96,6 +96,7 @@
wire grst = sys_rst_i;
wire gclk = sys_clk_i;
wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;
+ wire oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);

// --- INSTANTIATIONS -------------------------------------

@@ -121,7 +122,8 @@
.sys_int_i (sys_int_i),
.gclk (gclk),
.grst (grst),
- .gena (gena));
+ .gena (gena),
+ .oena (oena));

aeMB_ctrl
ctrl (/*AUTOINST*/
@@ -239,6 +241,9 @@

/*
$Log: aeMB_edk32.v,v $
+ Revision 1.14 2008/01/19 16:01:22 sybreon
+ Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)
+
Revision 1.13 2007/12/25 22:15:09 sybreon
Stalls pipeline on MUL/BSF instructions results in minor speed improvements.




1.9 aemb/rtl/verilog/aeMB_ibuf.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_ibuf.v.diff?r1=1.8&r2=1.9

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_ibuf.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_ibuf.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- aeMB_ibuf.v 25 Dec 2007 22:15:09 -0000 1.8
+++ aeMB_ibuf.v 19 Jan 2008 16:01:22 -0000 1.9
@@ -1,4 +1,4 @@
-/* $Id: aeMB_ibuf.v,v 1.8 2007/12/25 22:15:09 sybreon Exp $
+/* $Id: aeMB_ibuf.v,v 1.9 2008/01/19 16:01:22 sybreon Exp $
**
** AEMB INSTRUCTION BUFFER
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -24,7 +24,7 @@
rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
// Inputs
rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
- grst, gena
+ grst, gena, oena
);
// INTERNAL
output [15:0] rIMM;
@@ -49,7 +49,7 @@
input sys_int_i;

// SYSTEM
- input gclk, grst, gena;
+ input gclk, grst, gena, oena; reg [15:0] rIMM; reg [4:0] rRA, rRD; @@ -144,13 +144,16 @@ rSTALL <= 1'h0; // End of automatics end else begin - rSTALL <= #1 !rSTALL & (fMUL | fBSF); + rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL); end endmodule // aeMB_ibuf /* $Log: aeMB_ibuf.v,v $ + Revision 1.9 2008/01/19 16:01:22 sybreon + Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) + Revision 1.8 2007/12/25 22:15:09 sybreon Stalls pipeline on MUL/BSF instructions results in minor speed improvements.