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From: cvs at opencores.org<cvs@o...>
Date: Sat Dec 29 01:31:48 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/12 29:01:31

Modified: aemb/rtl/verilog aeMB2_sim.v
Log:
Minor cleanup




Revision Changes Path
1.2 aemb/rtl/verilog/aeMB2_sim.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_sim.v.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB2_sim.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_sim.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- aeMB2_sim.v 18 Dec 2007 18:54:36 -0000 1.1
+++ aeMB2_sim.v 29 Dec 2007 00:31:48 -0000 1.2
@@ -1,7 +1,6 @@
-/* $Id: aeMB2_sim.v,v 1.1 2007/12/18 18:54:36 sybreon Exp $
+/* $Id: aeMB2_sim.v,v 1.2 2007/12/29 00:31:48 sybreon Exp $
**
** AEMB2 SIMULATION WRAPPER
-**
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
**
** This file is part of AEMB.
@@ -42,35 +41,35 @@

/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
- output [6:2] cwb_adr_o; // From cpu of aeMB2_edk32.v
- output [31:0] cwb_dat_o; // From cpu of aeMB2_edk32.v
- output [3:0] cwb_sel_o; // From cpu of aeMB2_edk32.v
- output cwb_stb_o; // From cpu of aeMB2_edk32.v
- output [1:0] cwb_tga_o; // From cpu of aeMB2_edk32.v
- output cwb_wre_o; // From cpu of aeMB2_edk32.v
- output [DWB-1:2] dwb_adr_o; // From cpu of aeMB2_edk32.v
- output dwb_cyc_o; // From cpu of aeMB2_edk32.v
- output [31:0] dwb_dat_o; // From cpu of aeMB2_edk32.v
- output [3:0] dwb_sel_o; // From cpu of aeMB2_edk32.v
- output dwb_stb_o; // From cpu of aeMB2_edk32.v
- output dwb_tga_o; // From cpu of aeMB2_edk32.v
- output dwb_wre_o; // From cpu of aeMB2_edk32.v
- output [IWB-1:2] iwb_adr_o; // From cpu of aeMB2_edk32.v
- output iwb_stb_o; // From cpu of aeMB2_edk32.v
- output iwb_tga_o; // From cpu of aeMB2_edk32.v
- output iwb_wre_o; // From cpu of aeMB2_edk32.v
+ output [6:2] cwb_adr_o; // From sim of aeMB2_edk32.v
+ output [31:0] cwb_dat_o; // From sim of aeMB2_edk32.v
+ output [3:0] cwb_sel_o; // From sim of aeMB2_edk32.v
+ output cwb_stb_o; // From sim of aeMB2_edk32.v
+ output [1:0] cwb_tga_o; // From sim of aeMB2_edk32.v
+ output cwb_wre_o; // From sim of aeMB2_edk32.v
+ output [DWB-1:2] dwb_adr_o; // From sim of aeMB2_edk32.v
+ output dwb_cyc_o; // From sim of aeMB2_edk32.v
+ output [31:0] dwb_dat_o; // From sim of aeMB2_edk32.v
+ output [3:0] dwb_sel_o; // From sim of aeMB2_edk32.v
+ output dwb_stb_o; // From sim of aeMB2_edk32.v
+ output dwb_tga_o; // From sim of aeMB2_edk32.v
+ output dwb_wre_o; // From sim of aeMB2_edk32.v
+ output [IWB-1:2] iwb_adr_o; // From sim of aeMB2_edk32.v
+ output iwb_stb_o; // From sim of aeMB2_edk32.v
+ output iwb_tga_o; // From sim of aeMB2_edk32.v
+ output iwb_wre_o; // From sim of aeMB2_edk32.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
- input cwb_ack_i; // To cpu of aeMB2_edk32.v
- input [31:0] cwb_dat_i; // To cpu of aeMB2_edk32.v
- input dwb_ack_i; // To cpu of aeMB2_edk32.v
- input [31:0] dwb_dat_i; // To cpu of aeMB2_edk32.v
- input iwb_ack_i; // To cpu of aeMB2_edk32.v
- input [31:0] iwb_dat_i; // To cpu of aeMB2_edk32.v
- input sys_clk_i; // To cpu of aeMB2_edk32.v
- input sys_int_i; // To cpu of aeMB2_edk32.v
- input sys_rst_i; // To cpu of aeMB2_edk32.v
+ input cwb_ack_i; // To sim of aeMB2_edk32.v
+ input [31:0] cwb_dat_i; // To sim of aeMB2_edk32.v
+ input dwb_ack_i; // To sim of aeMB2_edk32.v
+ input [31:0] dwb_dat_i; // To sim of aeMB2_edk32.v
+ input iwb_ack_i; // To sim of aeMB2_edk32.v
+ input [31:0] iwb_dat_i; // To sim of aeMB2_edk32.v
+ input sys_clk_i; // To sim of aeMB2_edk32.v
+ input sys_int_i; // To sim of aeMB2_edk32.v
+ input sys_rst_i; // To sim of aeMB2_edk32.v
// End of automatics
/*AUTOWIRE*/

@@ -322,10 +321,12 @@

// synopsys translate_on

-
endmodule // aeMB2_sim

/* $Log: aeMB2_sim.v,v $ +/* Revision 1.2 2007/12/29 00:31:48 sybreon +/* Minor cleanup +/* /* Revision 1.1 2007/12/18 18:54:36 sybreon /* Partitioned simulation model. /* */ \ No newline at end of file