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From: cvs at opencores.org<cvs@o...>
Date: Tue Dec 25 23:15:09 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/12 25:23:15

Modified: aemb/rtl/verilog aeMB_edk32.v aeMB_ibuf.v aeMB_xecu.v
Log:
Stalls pipeline on MUL/BSF instructions results in minor speed improvements.


Revision Changes Path
1.13 aemb/rtl/verilog/aeMB_edk32.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_edk32.v.diff?r1=1.12&r2=1.13

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_edk32.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_edk32.v,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -b -r1.12 -r1.13
--- aeMB_edk32.v 23 Dec 2007 20:40:44 -0000 1.12
+++ aeMB_edk32.v 25 Dec 2007 22:15:09 -0000 1.13
@@ -1,4 +1,4 @@
-/* $Id: aeMB_edk32.v,v 1.12 2007/12/23 20:40:44 sybreon Exp $
+/* $Id: aeMB_edk32.v,v 1.13 2007/12/25 22:15:09 sybreon Exp $
**
** AEMB EDK 3.2 Compatible Core
** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -86,6 +86,7 @@
wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
+ wire rSTALL; // From ibuf of aeMB_ibuf.v
wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
// End of automatics

@@ -94,7 +95,7 @@

wire grst = sys_rst_i;
wire gclk = sys_clk_i;
- wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);
+ wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;

// --- INSTANTIATIONS -------------------------------------

@@ -109,6 +110,7 @@
.rOPC (rOPC[5:0]),
.rSIMM (rSIMM[31:0]),
.xIREG (xIREG[31:0]),
+ .rSTALL (rSTALL),
.iwb_stb_o (iwb_stb_o),
// Inputs
.rBRA (rBRA),
@@ -221,6 +223,7 @@
.rBRA (rBRA),
.rDLY (rDLY),
.rALT (rALT[10:0]),
+ .rSTALL (rSTALL),
.rSIMM (rSIMM[31:0]),
.rIMM (rIMM[15:0]),
.rOPC (rOPC[5:0]),
@@ -236,6 +239,9 @@

/*
$Log: aeMB_edk32.v,v $
+ Revision 1.13 2007/12/25 22:15:09 sybreon
+ Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
+
Revision 1.12 2007/12/23 20:40:44 sybreon
Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.




1.8 aemb/rtl/verilog/aeMB_ibuf.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_ibuf.v.diff?r1=1.7&r2=1.8

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_ibuf.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_ibuf.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- aeMB_ibuf.v 22 Nov 2007 15:11:15 -0000 1.7
+++ aeMB_ibuf.v 25 Dec 2007 22:15:09 -0000 1.8
@@ -1,54 +1,27 @@
-// $Id: aeMB_ibuf.v,v 1.7 2007/11/22 15:11:15 sybreon Exp $
-//
-// AEMB INSTRUCTION BUFFER
-//
-// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
-//
-// This file is part of AEMB.
-//
-// AEMB is free software: you can redistribute it and/or modify it
-// under the terms of the GNU Lesser General Public License as
-// published by the Free Software Foundation, either version 3 of the
-// License, or (at your option) any later version.
-//
-// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see <http://www.gnu.org/licenses/>. -// -// $Log: aeMB_ibuf.v,v $ -// Revision 1.7 2007/11/22 15:11:15 sybreon -// Change interrupt to positive level triggered interrupts. -// -// Revision 1.6 2007/11/14 23:39:51 sybreon -// Fixed interrupt signal synchronisation. -// -// Revision 1.5 2007/11/14 22:14:34 sybreon -// Changed interrupt handling system (reported by M. Ettus). -// -// Revision 1.4 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.3 2007/11/03 08:34:55 sybreon -// Minor code cleanup. -// -// Revision 1.2 2007/11/02 19:20:58 sybreon -// Added better (beta) interrupt support. -// Changed MSR_IE to disabled at reset as per MB docs. -// -// Revision 1.1 2007/11/02 03:25:40 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// +/* $Id: aeMB_ibuf.v,v 1.8 2007/12/25 22:15:09 sybreon Exp $ +** +** AEMB INSTRUCTION BUFFER +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...> +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see <http://www.gnu.org/licenses/>. +*/ module aeMB_ibuf (/*AUTOARG*/ // Outputs - rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, iwb_stb_o, + rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o, // Inputs rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk, grst, gena @@ -60,6 +33,7 @@ output [5:0] rOPC; output [31:0] rSIMM; output [31:0] xIREG; + output rSTALL; input rBRA; //input [1:0] rXCE; @@ -89,6 +63,7 @@ assign iwb_stb_o = 1'b1; reg [31:0] rSIMM, xSIMM; + reg rSTALL; wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08 wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10 @@ -155,5 +130,52 @@ rSIMM <= #1 xSIMM; end + // --- STALL FOR MUL/BSF ----------------------------------- + + wire [5:0] wOPC = xIREG[31:26]; + + wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30); + wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31); + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rSTALL <= 1'h0; + // End of automatics + end else begin + rSTALL <= #1 !rSTALL & (fMUL | fBSF); + end endmodule // aeMB_ibuf + +/* + $Log: aeMB_ibuf.v,v $ + Revision 1.8 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.7 2007/11/22 15:11:15 sybreon + Change interrupt to positive level triggered interrupts. + + Revision 1.6 2007/11/14 23:39:51 sybreon + Fixed interrupt signal synchronisation. + + Revision 1.5 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.4 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:40 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. +*/ \ No newline at end of file 1.10 aemb/rtl/verilog/aeMB_xecu.v http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_xecu.v.diff?r1=1.9&r2=1.10 (In the diff below, changes in quantity of whitespace are not shown.) Index: aeMB_xecu.v =================================================================== RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_xecu.v,v retrieving revision 1.9 retrieving revision 1.10 diff -u -b -r1.9 -r1.10 --- aeMB_xecu.v 30 Nov 2007 16:42:51 -0000 1.9 +++ aeMB_xecu.v 25 Dec 2007 22:15:09 -0000 1.10 @@ -1,56 +1,23 @@ -// $Id: aeMB_xecu.v,v 1.9 2007/11/30 16:42:51 sybreon Exp $ -// -// AEMB MAIN EXECUTION ALU -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...> -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see <http://www.gnu.org/licenses/>. -// -// $Log: aeMB_xecu.v,v $ -// Revision 1.9 2007/11/30 16:42:51 sybreon -// Minor code cleanup. -// -// Revision 1.8 2007/11/16 21:52:03 sybreon -// Added fsl_tag_o to FSL bus (tag either address or data). -// -// Revision 1.7 2007/11/14 22:14:34 sybreon -// Changed interrupt handling system (reported by M. Ettus). -// -// Revision 1.6 2007/11/10 16:39:38 sybreon -// Upgraded license to LGPLv3. -// Significant performance optimisations. -// -// Revision 1.5 2007/11/09 20:51:52 sybreon -// Added GET/PUT support through a FSL bus. -// -// Revision 1.4 2007/11/08 14:17:47 sybreon -// Parameterised optional components. -// -// Revision 1.3 2007/11/03 08:34:55 sybreon -// Minor code cleanup. -// -// Revision 1.2 2007/11/02 19:20:58 sybreon -// Added better (beta) interrupt support. -// Changed MSR_IE to disabled at reset as per MB docs. -// -// Revision 1.1 2007/11/02 03:25:41 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// +/* $Id: aeMB_xecu.v,v 1.10 2007/12/25 22:15:09 sybreon Exp $ +** +** AEMB MAIN EXECUTION ALU +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...> +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see <http://www.gnu.org/licenses/>. +*/ module aeMB_xecu (/*AUTOARG*/ // Outputs @@ -58,7 +25,7 @@ rMSR_IE, rMSR_BIP, // Inputs rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT, - rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena + rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena ); parameter DW=32; @@ -85,6 +52,7 @@ input rBRA, rDLY; input [10:0] rALT; + input rSTALL; input [31:0] rSIMM; input [15:0] rIMM; input [5:0] rOPC; @@ -193,11 +161,22 @@ // --- MULTIPLIER ------------------------------------------ // TODO: 2 stage multiplier - reg [31:0] rRES_MUL; + reg [31:0] rRES_MUL, rRES_MUL0, xRES_MUL; always @(/*AUTOSENSE*/rOPA or rOPB) begin - rRES_MUL <= (rOPA * rOPB); + xRES_MUL <= (rOPA * rOPB); end + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rRES_MUL <= 32'h0; + // End of automatics + end else if (rSTALL) begin + rRES_MUL <= #1 xRES_MUL; + end + + // --- BARREL SHIFTER -------------------------------------- reg [31:0] rRES_BSF; @@ -248,11 +227,27 @@ 5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]}; endcase // case (rOPB[4:0]) - always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL) + reg [31:0] rBSRL, rBSRA, rBSLL; + + always @(posedge gclk) + if (grst) begin + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + rBSLL <= 32'h0; + rBSRA <= 32'h0; + rBSRL <= 32'h0; + // End of automatics + end else if (rSTALL) begin + rBSRL <= #1 xBSRL; + rBSRA <= #1 xBSRA; + rBSLL <= #1 xBSLL; + end + + always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL) case (rALT[10:9]) - 2'd0: rRES_BSF <= xBSRL; - 2'd1: rRES_BSF <= xBSRA; - 2'd2: rRES_BSF <= xBSLL; + 2'd0: rRES_BSF <= rBSRL; + 2'd1: rRES_BSF <= rBSRA; + 2'd2: rRES_BSF <= rBSLL; default: rRES_BSF <= 32'hX; endcase // case (rALT[10:9]) @@ -377,3 +372,41 @@ end endmodule // aeMB_xecu + +/* + $Log: aeMB_xecu.v,v $ + Revision 1.10 2007/12/25 22:15:09 sybreon + Stalls pipeline on MUL/BSF instructions results in minor speed improvements. + + Revision 1.9 2007/11/30 16:42:51 sybreon + Minor code cleanup. + + Revision 1.8 2007/11/16 21:52:03 sybreon + Added fsl_tag_o to FSL bus (tag either address or data). + + Revision 1.7 2007/11/14 22:14:34 sybreon + Changed interrupt handling system (reported by M. Ettus). + + Revision 1.6 2007/11/10 16:39:38 sybreon + Upgraded license to LGPLv3. + Significant performance optimisations. + + Revision 1.5 2007/11/09 20:51:52 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.4 2007/11/08 14:17:47 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/03 08:34:55 sybreon + Minor code cleanup. + + Revision 1.2 2007/11/02 19:20:58 sybreon + Added better (beta) interrupt support. + Changed MSR_IE to disabled at reset as per MB docs. + + Revision 1.1 2007/11/02 03:25:41 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. + +*/ \ No newline at end of file