OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Sun Dec 23 21:40:52 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...

Date: 00/07/12 23:21:40

Modified: aemb/sim/verilog edk32.v Log: Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. Revision Changes Path 1.12 aemb/sim/verilog/edk32.v http://www.opencores.org/cvsweb.shtml/aemb/sim/verilog/edk32.v.diff?r1=1.11&r2=1.12 (In the diff below, changes in quantity of whitespace are not shown.) Index: edk32.v =================================================================== RCS file: /cvsroot/sybreon/aemb/sim/verilog/edk32.v,v retrieving revision 1.11 retrieving revision 1.12 diff -u -b -r1.11 -r1.12 --- edk32.v 11 Dec 2007 00:44:31 -0000 1.11 +++ edk32.v 23 Dec 2007 20:40:51 -0000 1.12 @@ -1,62 +1,23 @@ -// $Id: edk32.v,v 1.11 2007/12/11 00:44:31 sybreon Exp $ -// -// AEMB EDK 3.2 Compatible Core TEST -// -// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...> -// -// This file is part of AEMB. -// -// AEMB is free software: you can redistribute it and/or modify it -// under the terms of the GNU Lesser General Public License as -// published by the Free Software Foundation, either version 3 of the -// License, or (at your option) any later version. -// -// AEMB is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General -// Public License for more details. -// -// You should have received a copy of the GNU Lesser General Public -// License along with AEMB. If not, see <http://www.gnu.org/licenses/>. -// -// $Log: edk32.v,v $ -// Revision 1.11 2007/12/11 00:44:31 sybreon -// Modified for AEMB2 -// -// Revision 1.10 2007/11/30 17:08:30 sybreon -// Moved simulation kernel into code. -// -// Revision 1.9 2007/11/20 18:36:00 sybreon -// Removed unnecessary byte acrobatics with VMEM data. -// -// Revision 1.8 2007/11/18 19:41:45 sybreon -// Minor simulation fixes. -// -// Revision 1.7 2007/11/14 22:11:41 sybreon -// Added posedge/negedge bus interface. -// Modified interrupt test system. -// -// Revision 1.6 2007/11/13 23:37:28 sybreon -// Updated simulation to also check BRI 0x00 instruction. -// -// Revision 1.5 2007/11/09 20:51:53 sybreon -// Added GET/PUT support through a FSL bus. -// -// Revision 1.4 2007/11/08 14:18:00 sybreon -// Parameterised optional components. -// -// Revision 1.3 2007/11/05 10:59:31 sybreon -// Added random seed for simulation. -// -// Revision 1.2 2007/11/02 19:16:10 sybreon -// Added interrupt simulation. -// Changed "human readable" simulation output. -// -// Revision 1.1 2007/11/02 03:25:45 sybreon -// New EDK 3.2 compatible design with optional barrel-shifter and multiplier. -// Fixed various minor data hazard bugs. -// Code compatible with -O0/1/2/3/s generated code. -// +/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $ +** +** AEMB EDK 3.2 Compatible Core TEST +** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...> +** +** This file is part of AEMB. +** +** AEMB is free software: you can redistribute it and/or modify it +** under the terms of the GNU Lesser General Public License as +** published by the Free Software Foundation, either version 3 of the +** License, or (at your option) any later version. +** +** AEMB is distributed in the hope that it will be useful, but WITHOUT +** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General +** Public License for more details. +** +** You should have received a copy of the GNU Lesser General Public +** License along with AEMB. If not, see <http://www.gnu.org/licenses/>. +*/ `define AEMB_SIMULATION_KERNEL @@ -219,7 +180,7 @@ always @(posedge sys_clk_i) begin // Interrupt Monitors - if (!dut.rMSR_IE) begin + if (!dut.cpu.rMSR_IE) begin rnd = $random % 30; inttime = $stime + 1000 + (rnd*rnd * 10); end @@ -232,7 +193,7 @@ $finish; end if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0; - if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin + if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin svc = 1; //$display("\nLATENCY: ", ($stime - inttime)/10); end @@ -255,7 +216,7 @@ // INTERNAL WIRING //////////////////////////////////////////////////// - aeMB_edk32 #(16,16) + aeMB_sim #(16,16) dut ( .sys_int_i(sys_int_i), .dwb_ack_i(dwb_ack_i), @@ -282,3 +243,46 @@ ); endmodule // edk32 + +/* + $Log: edk32.v,v $ + Revision 1.12 2007/12/23 20:40:51 sybreon + Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models. + + Revision 1.11 2007/12/11 00:44:31 sybreon + Modified for AEMB2 + + Revision 1.10 2007/11/30 17:08:30 sybreon + Moved simulation kernel into code. + + Revision 1.9 2007/11/20 18:36:00 sybreon + Removed unnecessary byte acrobatics with VMEM data. + + Revision 1.8 2007/11/18 19:41:45 sybreon + Minor simulation fixes. + + Revision 1.7 2007/11/14 22:11:41 sybreon + Added posedge/negedge bus interface. + Modified interrupt test system. + + Revision 1.6 2007/11/13 23:37:28 sybreon + Updated simulation to also check BRI 0x00 instruction. + + Revision 1.5 2007/11/09 20:51:53 sybreon + Added GET/PUT support through a FSL bus. + + Revision 1.4 2007/11/08 14:18:00 sybreon + Parameterised optional components. + + Revision 1.3 2007/11/05 10:59:31 sybreon + Added random seed for simulation. + + Revision 1.2 2007/11/02 19:16:10 sybreon + Added interrupt simulation. + Changed "human readable" simulation output. + + Revision 1.1 2007/11/02 03:25:45 sybreon + New EDK 3.2 compatible design with optional barrel-shifter and multiplier. + Fixed various minor data hazard bugs. + Code compatible with -O0/1/2/3/s generated code. + */ \ No newline at end of file