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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Dec 22 17:08:09 CET 2007
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/07/12 22:17:08 Added: jop/vhdl/simulation bytecode.vhd
Log:
symbolic bytecode
Revision Changes Path
1.1 jop/vhdl/simulation/bytecode.vhd
http://www.opencores.org/cvsweb.shtml/jop/vhdl/simulation/bytecode.vhd?rev=1.1&content-type=text/x-cvsweb-markup
Index: bytecode.vhd
===================================================================
--
-- bytecode.vhd
--
-- Show bytecode mnemonic in the simulation
--
-- Author: Martin Schoeberl martin@j...
--
--
--
-- 2007-12-22 creation
--
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bytecode is
port (jinstr : in std_logic_vector(7 downto 0));
end bytecode;
architecture sim of bytecode is
type bcval is (iadd, isub
);
signal val : bcval;
begin
val <= bcval'val(to_integer(unsigned(jinstr)));
end sim;
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