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From: cvs at opencores.org<cvs@o...>
Date: Sun Dec 16 21:38:06 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/12 16:21:38

Modified: aemb/rtl/verilog aeMB2_aslu.v aeMB2_ofid.v
Log:
Minor optimisations.


Revision Changes Path
1.6 aemb/rtl/verilog/aeMB2_aslu.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_aslu.v.diff?r1=1.5&r2=1.6

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB2_aslu.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_aslu.v,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- aeMB2_aslu.v 16 Dec 2007 03:25:37 -0000 1.5
+++ aeMB2_aslu.v 16 Dec 2007 20:38:06 -0000 1.6
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_aslu.v,v 1.5 2007/12/16 03:25:37 sybreon Exp $
+/* $Id: aeMB2_aslu.v,v 1.6 2007/12/16 20:38:06 sybreon Exp $
**
** AEMB2 INTEGER ARITHMETIC SHIFT LOGIC UNIT
**
@@ -422,10 +422,10 @@
wire fMTS = (rOPC == 6'o45) & rIMM[14];
wire fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);

- always @(/*AUTOSENSE*/fADDC or rIMM or rMSR_C or rOPC or rRES_ADDC
- or rRES_SFTC)
- //case (rALU_OF[1:0])
- case (rOPC[5:4])
+ always @(/*AUTOSENSE*/fADDC or rALU_OF or rIMM or rMSR_C or rOPC
+ or rRES_ADDC or rRES_SFTC)
+ case (rALU_OF[1:0])
+ //case (rOPC[5:4])
3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C; // ADD/SUB
3'o2: case (rOPC[2:0])
3'o5: xMSR_C <= (rIMM[14]) ? rOPC[2] : rMSR_C; // MTS
@@ -554,6 +554,9 @@
endmodule // aeMB2_aslu

/* $Log: aeMB2_aslu.v,v $
+/* Revision 1.6 2007/12/16 20:38:06 sybreon
+/* Minor optimisations.
+/*
/* Revision 1.5 2007/12/16 03:25:37 sybreon
/* Some optimisations.
/*



1.2 aemb/rtl/verilog/aeMB2_ofid.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB2_ofid.v.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB2_ofid.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB2_ofid.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- aeMB2_ofid.v 16 Dec 2007 03:24:20 -0000 1.1
+++ aeMB2_ofid.v 16 Dec 2007 20:38:06 -0000 1.2
@@ -1,4 +1,4 @@
-/* $Id: aeMB2_ofid.v,v 1.1 2007/12/16 03:24:20 sybreon Exp $
+/* $Id: aeMB2_ofid.v,v 1.2 2007/12/16 20:38:06 sybreon Exp $
**
** AEMB2 COMBINED OPERAND FETCH & INSTRUCTION DECODE
**
@@ -169,7 +169,7 @@
synchronisation and compatibility with single threaded apps. There
isn't a reason why it needs to stay this way if things change. */

- wire fINT = !rFIM & !rBRA[1] & rINT & pha_i;
+ wire fINT =!rFIM & !rBRA[1] & rINT & pha_i;

/* Latch onto the operand */
// TODO: Optimise
@@ -329,6 +329,9 @@
endmodule // aeMB2_ofid

/* $Log: aeMB2_ofid.v,v $
+/* Revision 1.2 2007/12/16 20:38:06 sybreon
+/* Minor optimisations.
+/*
/* Revision 1.1 2007/12/16 03:24:20 sybreon
/* Combined ID/OF blocks.
/* */
\ No newline at end of file