Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Fri Nov 30 17:44:40 CET 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/11 30:17:44

Modified: aemb/rtl/verilog aeMB_ctrl.v
Log:
Minor code cleanup.


Revision Changes Path
1.10 aemb/rtl/verilog/aeMB_ctrl.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_ctrl.v.diff?r1=1.9&r2=1.10

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_ctrl.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_ctrl.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- aeMB_ctrl.v 15 Nov 2007 09:26:43 -0000 1.9
+++ aeMB_ctrl.v 30 Nov 2007 16:44:40 -0000 1.10
@@ -1,4 +1,4 @@
-// $Id: aeMB_ctrl.v,v 1.9 2007/11/15 09:26:43 sybreon Exp $
+// $Id: aeMB_ctrl.v,v 1.10 2007/11/30 16:44:40 sybreon Exp $
//
// AEMB CONTROL UNIT
//
@@ -20,6 +20,9 @@
// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
//
// $Log: aeMB_ctrl.v,v $
+// Revision 1.10 2007/11/30 16:44:40 sybreon
+// Minor code cleanup.
+//
// Revision 1.9 2007/11/15 09:26:43 sybreon
// Fixed minor typo causing synthesis failure.
//
@@ -66,10 +69,7 @@
output [1:0] rMXSRC, rMXTGT, rMXALT;
output [2:0] rMXALU;
output [4:0] rRW;
- //output rDWBSTB;
- //output rFSLSTB;

- //input [1:0] rXCE;
input rDLY;
input [15:0] rIMM;
input [10:0] rALT;
@@ -164,28 +164,6 @@

// --- OPERAND SELECTOR ---------------------------------

- /*
- wire fRDWE = |rRW;
- wire fAFWD_M = (rRW == rRA) & (rMXDST == 2'o2) & fRDWE;
- wire fBFWD_M = (rRW == rRB) & (rMXDST == 2'o2) & fRDWE;
- wire fAFWD_R = (rRW == rRA) & (rMXDST == 2'o0) & fRDWE;
- wire fBFWD_R = (rRW == rRB) & (rMXDST == 2'o0) & fRDWE;
-
- assign rMXSRC = (fBRU | fBCC) ? 2'o3 : // PC
- (fAFWD_M) ? 2'o2: // RAM
- (fAFWD_R) ? 2'o1: // FWD
- 2'o0; // REG
-
- assign rMXTGT = (rOPC[3]) ? 2'o3 : // IMM
- (fBFWD_M) ? 2'o2 : // RAM
- (fBFWD_R) ? 2'o1 : // FWD
- 2'o0; // REG
-
- assign rMXALT = (fAFWD_M) ? 2'o2 : // RAM
- (fAFWD_R) ? 2'o1 : // FWD
- 2'o0; // REG
- */
-
wire wRDWE = |xRW;
wire wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
wire wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
@@ -214,24 +192,10 @@
xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
(wAFWD_R) ? 2'o1 : // FWD
2'o0; // REG
- end
+ end // else: !if(rBRA)

// --- ALU CONTROL ---------------------------------------

- /*
- reg [2:0] rMXALU;
- always @(fBRA or fBSF or fDIV or fLOG or fMOV or fMUL
- or fSFT) begin
- rMXALU <= (fBRA | fMOV) ? 3'o3 :
- (fSFT) ? 3'o2 :
- (fLOG) ? 3'o1 :
- (fMUL) ? 3'o4 :
- (fBSF) ? 3'o5 :
- (fDIV) ? 3'o6 :
- 3'o0;
- end
- */
-
reg [2:0] rMXALU, xMXALU;
always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV @@ -250,7 +214,7 @@ (wBSF) ? 3'o5 : (wDIV) ? 3'o6 : 3'o0; - end + end // else: !if(rBRA) // --- DELAY SLOT REGISTERS ------------------------------ @@ -265,20 +229,6 @@ xRW <= 5'h0; // End of automatics end else begin - /* - case (rXCE) - 2'o2: xMXDST <= 2'o1; - default: xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 : - (fLOD | fGET) ? 2'o2 : - (fBRU) ? 2'o1 : - 2'o0; - endcase - - case (rXCE) - 2'o2: xRW <= 5'd14; - default: xRW <= rRD; - endcase - */ xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 : (fLOD | fGET) ? 2'o2 : (fBRU) ? 2'o1 : @@ -372,7 +322,7 @@ rMXTGT <= 2'h0; rRW <= 5'h0; // End of automatics - end else if (gena) begin + end else if (gena) begin // if (grst) //rPCLNK <= #1 xPCLNK; rMXDST <= #1 xMXDST; rRW <= #1 xRW;