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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Fri Nov 30 17:42:51 CET 2007
    Subject: [cvs-checkins] MODIFIED: aemb ...
    Top
    Date: 00/07/11 30:17:42

    Modified: aemb/rtl/verilog aeMB_xecu.v
    Log:
    Minor code cleanup.


    Revision Changes Path
    1.9 aemb/rtl/verilog/aeMB_xecu.v

    http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_xecu.v.diff?r1=1.8&r2=1.9

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: aeMB_xecu.v
    ===================================================================
    RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_xecu.v,v
    retrieving revision 1.8
    retrieving revision 1.9
    diff -u -b -r1.8 -r1.9
    --- aeMB_xecu.v 16 Nov 2007 21:52:03 -0000 1.8
    +++ aeMB_xecu.v 30 Nov 2007 16:42:51 -0000 1.9
    @@ -1,4 +1,4 @@
    -// $Id: aeMB_xecu.v,v 1.8 2007/11/16 21:52:03 sybreon Exp $
    +// $Id: aeMB_xecu.v,v 1.9 2007/11/30 16:42:51 sybreon Exp $
    //
    // AEMB MAIN EXECUTION ALU
    //
    @@ -20,6 +20,9 @@
    // License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
    //
    // $Log: aeMB_xecu.v,v $
    +// Revision 1.9 2007/11/30 16:42:51 sybreon
    +// Minor code cleanup.
    +//
    // Revision 1.8 2007/11/16 21:52:03 sybreon
    // Added fsl_tag_o to FSL bus (tag either address or data).
    //
    @@ -75,7 +78,6 @@
    output [3:0] rDWBSEL;
    output rMSR_IE;
    output rMSR_BIP;
    - //input [1:0] rXCE;
    input [31:0] rREGA, rREGB;
    input [1:0] rMXSRC, rMXTGT;
    input [4:0] rRA, rRB;
    @@ -89,8 +91,6 @@
    input [4:0] rRD;
    input [31:0] rDWBDI;
    input [31:2] rPC;
    - //input [31:0] rRES_MUL; // External Multiplier
    - //input [31:0] rRES_BSF; // External Barrel Shifter

    // SYSTEM
    input gclk, grst, gena;
    @@ -191,6 +191,7 @@
    rOPA;

    // --- MULTIPLIER ------------------------------------------
    + // TODO: 2 stage multiplier

    reg [31:0] rRES_MUL;
    always @(/*AUTOSENSE*/rOPA or rOPB) begin
    @@ -282,10 +283,10 @@
    wire fRTID = (rOPC == 6'o55) & rRD[0];
    wire fRTBD = (rOPC == 6'o55) & rRD[1];
    wire fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
    - wire fXCE = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
    + wire fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);

    - always @(/*AUTOSENSE*/fMTS or fRTID or fXCE or rMSR_IE or rOPA)
    - xMSR_IE <= (fXCE) ? 1'b0 :
    + always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
    + xMSR_IE <= (fINT) ? 1'b0 :
    (fRTID) ? 1'b1 :
    (fMTS) ? rOPA[1] :
    rMSR_IE;



     
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