|
Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Nov 29 04:50:36 CET 2007
Subject: [cvs-checkins] MODIFIED: mips789 ...
Date: 00/07/11 29:04:50 Modified: mips789/rtl/verilog EXEC_stage.v RF_components.v ctl_fsm.v
dvc.v forward.v mem_module.v mips789_defs.v
mips_uart.v ulit.v
Log:
no message
Revision Changes Path
1.10 mips789/rtl/verilog/EXEC_stage.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/EXEC_stage.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: EXEC_stage.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/EXEC_stage.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- EXEC_stage.v 26 Nov 2007 13:46:21 -0000 1.9
+++ EXEC_stage.v 29 Nov 2007 03:50:36 -0000 1.10
@@ -65,7 +65,7 @@
wire [31:0] BUS476;
- big_alu MIPS_alu
+ mips_alu MIPS_alu
(
.a(BUS476),
.b(BUS468),
@@ -140,7 +140,7 @@
endmodule
-module big_alu(clk,rst,a,b,c,ctl);
+module mips_alu(clk,rst,a,b,c,ctl);
input clk,rst ;
input [31:0] a,b ;
output [31:0] c ;
@@ -235,11 +235,13 @@
//This file is based on YACC ->alu.v and UCORE ->alu.v
-module alu (a,b,alu_out,alu_func);
+module alu (
+ input [31:0] a,
+ input [31:0]b,
+ output reg [31:0] alu_out,
+ input [4:0] alu_func
+ );
- input [31:0] a,b;
- output reg [31:0] alu_out;
- input [4:0] alu_func;
reg [32:0] sum;
always @(*)
@@ -294,8 +296,7 @@
endmodule
-module
- shifter_tak(
+module shifter_tak(
input [31:0] a,
output reg [31:0] shift_out,
input [4:0] shift_func,//connect to alu_func_ctl
1.9 mips789/rtl/verilog/RF_components.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/RF_components.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: RF_components.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/RF_components.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- RF_components.v 26 Nov 2007 13:46:21 -0000 1.8
+++ RF_components.v 29 Nov 2007 03:50:36 -0000 1.9
@@ -21,21 +21,17 @@
wire [25:0] instr25_0;
assign instr25_0 = ins_i[25:0] ;
- wire[15:0] sign = {
- instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
- instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
- instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15],
- instr25_0[15],instr25_0[15],instr25_0[15],instr25_0[15]};
+ wire[15:0] sign = {16{instr25_0[15]}};
always @ (*)
case (ctl)
`EXT_SIGN :res ={sign,instr25_0[15:0]};//sign
`EXT_UNSIGN :res ={16'b0,instr25_0[15:0]};//zeroext
`EXT_J :res ={4'b0,instr25_0[25:0],2'b0};//jmp
- `EXT_B :res ={sign[13:0],instr25_0[15:0],2'B0};//brach
+ `EXT_B :res ={sign[13:0],instr25_0[15:0],2'B0};//branch
`EXT_SA :res ={27'b0,instr25_0[10:6]} ;//sll,srl
`EXT_S2H :res ={instr25_0[15:0],16'B0};//shift to high
- default: res=0;
+ default: res=32'bx;
endcase
endmodule
@@ -54,7 +50,7 @@
`CMP_BGTZ: res = ~s[31] && (|s[30:0]);
`CMP_BLEZ: res = s[31] |(~|s);
`CMP_BGEZ: res = ~s[31];
- default res=1'B0;
+ default res=1'Bx;
endcase
endmodule
@@ -72,20 +68,6 @@
);
wire [32:0] br_addr = pc + imm ;
- /*
- pc_gen i_pc_gen
- (
- .check(NET904),
- .ctl(pc_gen_ctl),
- .imm(ext_o),
- .irq(irq_addr_i),
- .pc(pc_i),
- .pc_next(pc_next),
- .pc_prectl(BUS1013),
- .s(rs_o),
- .zz_spc(zz_spc_i)
- );
- */
always @ (*)
if(pc_prectl == `PC_IGN )
begin
@@ -94,8 +76,8 @@
`PC_J : pc_next ={pc[31:28],imm[27:0]};
`PC_JR : pc_next = s;
`PC_BC : pc_next = (check)?({br_addr[31:0]}):(pc+4);
- `PC_NEXT : pc_next = pc+ 4 ;
- default pc_next = pc + 4;
+ default
+ /* `PC_NEXT :*/ pc_next = pc + 4 ;
endcase
end
else
@@ -103,8 +85,9 @@
case (pc_prectl)
`PC_KEP : pc_next=pc;
`PC_IRQ : pc_next=irq;
- `PC_RST : pc_next='d0;
- default pc_next =0;
+ default
+ /* `PC_RST : pc_next='d0;*/
+ pc_next =0;
endcase
end
@@ -143,6 +126,7 @@
output [31:0] qa;
output [31:0] qb;
reg [31:0]reg_bank[0:31];
+
integer i;
initial
begin
@@ -150,13 +134,12 @@
reg_bank[i]=0;
end
- assign qa=(r_rdaddress_a[4:0]==0)?0:
- ((r_wraddress==r_rdaddress_a)&&(1==r_wren))?r_data:
- reg_bank[r_rdaddress_a];
-
- assign qb=(r_rdaddress_b[4:0]==0)?0:
- ((r_wraddress==r_rdaddress_b)&&(1==r_wren))?r_data:
- reg_bank[r_rdaddress_b];
+ always@(posedge clock)
+ begin
+ r_data <=data;
+ r_wraddress<=wraddress;
+ r_wren<=wren;
+ end
always@(posedge clock)
if (~rd_clk_cls)
@@ -166,12 +149,15 @@
end
always@(posedge clock)
- begin
- r_data <=data;
- r_wraddress<=wraddress;
- r_wren<=wren;
- end
- always@(posedge clock)
if (r_wren)
reg_bank[r_wraddress] <= r_data ;
+
+ assign qa=(r_rdaddress_a[4:0]==0)?0:
+ ((r_wraddress==r_rdaddress_a)&&(1==r_wren))?r_data:
+ reg_bank[r_rdaddress_a];
+
+ assign qb=(r_rdaddress_b[4:0]==0)?0:
+ ((r_wraddress==r_rdaddress_b)&&(1==r_wren))?r_data:
+ reg_bank[r_rdaddress_b];
+
endmodule
1.9 mips789/rtl/verilog/ctl_fsm.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ctl_fsm.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ctl_fsm.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ctl_fsm.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- ctl_fsm.v 26 Nov 2007 13:46:21 -0000 1.8
+++ ctl_fsm.v 29 Nov 2007 03:50:36 -0000 1.9
@@ -13,273 +13,165 @@
`include "mips789_defs.v"
module ctl_FSM (
- clk, iack, id2ra_ctl_clr, id2ra_ctl_cls,
- id2ra_ins_clr, id2ra_ins_cls, id_cmd, irq,
- pc_prectl, ra2exec_ctl_clr, rst ,zz_is_nop
+ input clk,
+ input [2:0] id_cmd,
+ input irq,
+ input rst,
+ output reg iack,
+ output reg zz_is_nop,
+ output reg id2ra_ctl_clr,
+ output reg id2ra_ctl_cls,
+ output reg id2ra_ins_clr,
+ output reg id2ra_ins_cls,
+ output reg [3:0] pc_prectl,
+ output reg ra2exec_ctl_clr
);
-
parameter
-
- ID_CUR = 1,
- ID_LD = 5,
- ID_MUL = 2,
- ID_NOI = 6,
- ID_RET = 4,
- ONE = 1,
- PC_IGN = 1,
- PC_IRQ = 4,
- PC_KEP = 2,
- PC_RST = 8,
- ZERO = 0;
-
- input clk;
- input [2:0] id_cmd;
- input irq;
- input rst;
- output iack;
- output zz_is_nop;
- output id2ra_ctl_clr;
- output id2ra_ctl_cls;
- output id2ra_ins_clr;
- output id2ra_ins_cls;
- output [3:0] pc_prectl;
- output ra2exec_ctl_clr;
-
- wire clk;
- reg iack;
- reg zz_is_nop;
- reg id2ra_ctl_clr;
- reg id2ra_ctl_cls;
- reg id2ra_ins_clr;
- reg id2ra_ins_cls;
- wire [2:0] id_cmd;
- wire irq;
- reg [3:0] pc_prectl;
- reg ra2exec_ctl_clr;
- wire rst;
+ ID_CUR = `FSM_CUR, ID_LD = `FSM_LD ,
+ ID_MUL = `FSM_MUL, ID_NOI = `FSM_NOI,
+ ID_RET = `FSM_RET,
+
+ PC_IGN = `PC_IGN , PC_IRQ = `PC_IRQ,
+ PC_KEP = `PC_KEP , PC_RST = `PC_RST;
+
+ reg [5:0] delay_counter;
+ reg [4:0] CurrState ;
+ reg [4:0] NextState ;
reg riack;
+ always @(posedge clk) if (~rst) riack<=0; else riack<=iack;
- reg [5:0]delay_counter_Sreg0, next_delay_counter_Sreg0;
+ always @(*)
+ begin //deal with iack
+ case (CurrState )
+ `IRQ:iack=1'b1;
+ `RET:iack=1'b0;
+ //onlt this 2 states those will change the iack state
+ default iack=riack;
+ endcase
+ end
- reg [3:0] CurrState_Sreg0;
- reg [3:0] NextState_Sreg0;
+ always @ (posedge clk )
+ if (~rst)delay_counter <=0;
+ else
+ case (CurrState)
+ //any delay state can be added here
+ `MUL: delay_counter <=delay_counter + 1;
+ default : delay_counter <=0;
+ endcase
- always @ (*)
- begin : Sreg0_NextState
- case (CurrState_Sreg0)
+/////////////////////////////////////////////////////////
+// Finite State Machine
+//
+ /*Finite State Machine part1*/
+ always @ (posedge clk) if (~rst) CurrState <= `RST; else CurrState <= NextState ;
+
+ always @ (*)/*Finite State Machine part2*/
+ begin
+ case (CurrState)
`IDLE:
begin
- id2ra_ins_clr=ZERO;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ZERO;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr =ZERO;
- pc_prectl=PC_IGN;
- iack = riack;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- if ((irq)&&(~iack))
- NextState_Sreg0 = `IRQ;
- else
- if (id_cmd ==ID_NOI)
- NextState_Sreg0 = `NOI;
- else
- if (id_cmd==ID_CUR)
- NextState_Sreg0 = `CUR;
- else
- if (id_cmd==ID_MUL)
- NextState_Sreg0 = `MUL;
- else
- if (id_cmd==ID_LD)
- NextState_Sreg0 = `LD;
- else
- if (id_cmd==ID_RET)
- NextState_Sreg0 = `RET;
- else
- NextState_Sreg0 = `IDLE;
+ if (~rst) NextState = `RST;
+ else if ((irq)&&(~riack)) NextState = `IRQ;
+ else if (id_cmd ==ID_NOI) NextState = `NOI;
+ else if (id_cmd==ID_CUR) NextState = `CUR;
+ else if (id_cmd==ID_MUL) NextState = `MUL;
+ else if (id_cmd==ID_LD) NextState = `LD;
+ else if (id_cmd==ID_RET) NextState = `RET;
+ else NextState = `IDLE;
end
- `MUL:
+ `NOI:
begin
- id2ra_ins_clr=ONE;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ONE;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr=ZERO;
- pc_prectl =PC_KEP;
- iack = riack;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- NextState_Sreg0 = `D2_MUL_DLY;
- next_delay_counter_Sreg0 = 34;
- zz_is_nop =0;
+ if (id_cmd ==ID_NOI) NextState = `NOI;
+ else if (id_cmd==ID_CUR) NextState = `CUR;
+ else if (id_cmd==ID_MUL) NextState = `MUL;
+ else if (id_cmd==ID_LD) NextState = `LD;
+ else if (id_cmd==ID_RET) NextState = `RET;
+ else NextState = `IDLE;
+ end
+ `CUR: NextState = `NOI;
+ `RET: NextState = `IDLE;
+ `IRQ: NextState = `IDLE;
+ `RST: NextState = `IDLE;
+ `LD: NextState = `IDLE;
+ `MUL: NextState = (delay_counter==32)?`IDLE:`MUL;
+ default NextState =`IDLE;
+ endcase
end
- `CUR:
+
+ always @ (*)/*Finite State Machine part3*/
begin
- id2ra_ins_clr=ZERO;
- id2ra_ins_cls=ONE;
- id2ra_ctl_clr=ZERO;
- id2ra_ctl_cls=ONE;
- ra2exec_ctl_clr=ONE;
+ case (CurrState )
+ `IDLE: begin id2ra_ins_clr = 1'b0;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b0;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b0;
+ pc_prectl=PC_IGN;
+ zz_is_nop = 0;end
+ `MUL: begin
+ id2ra_ins_clr = 1'b1;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b1;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b0;
pc_prectl =PC_KEP;
- iack = riack;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- NextState_Sreg0 = `NOI;
- zz_is_nop = 1;
- end
- `RET:
- begin
- id2ra_ins_clr=ZERO;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ZERO;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr =ZERO;
+ zz_is_nop =0; end
+ `CUR: begin
+ id2ra_ins_clr = 1'b0;
+ id2ra_ins_cls = 1'b1;
+ id2ra_ctl_clr = 1'b0;
+ id2ra_ctl_cls = 1'b1;
+ ra2exec_ctl_clr = 1'b1;
+ pc_prectl =PC_KEP;
+ zz_is_nop = 1; end
+ `RET: begin id2ra_ins_clr = 1'b0;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b0;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b0;
pc_prectl =PC_IGN;
- iack =ZERO;
- riack =ZERO;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- NextState_Sreg0 = `IDLE;
- zz_is_nop = ZERO;
- end
- `IRQ:
- begin
- id2ra_ins_clr=ONE;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ONE;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr=ONE;
+ zz_is_nop = 1'b0; end
+ `IRQ: begin
+ id2ra_ins_clr = 1'b1;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b1;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b1;
pc_prectl =PC_IRQ;
- iack =ONE;
- riack=ONE;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- NextState_Sreg0 = `IDLE;
- zz_is_nop = ZERO;
- end
- `RST:
- begin
- id2ra_ins_clr=ONE;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ONE;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr=ONE;
+ zz_is_nop = 1'b0;end
+ `RST: begin
+ id2ra_ins_clr = 1'b1;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b1;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b1;
pc_prectl=PC_RST;
- iack=ZERO;
- zz_is_nop = ONE;
- riack=ZERO;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- NextState_Sreg0 = `IDLE;
- end
- `LD:
- begin
- id2ra_ins_clr=ONE;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ONE;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr=ZERO;
+ zz_is_nop = 1'b1; end
+ `LD:begin
+ id2ra_ins_clr = 1'b1;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b1;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b0;
pc_prectl =PC_KEP;
- iack=riack;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- NextState_Sreg0 = `IDLE;
- zz_is_nop = ZERO;
- end
- `NOI:
- begin
- id2ra_ins_clr=ZERO;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ZERO;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr =ZERO;
- iack=riack;
+ zz_is_nop = 1'b0;end
+ `NOI:begin
+ id2ra_ins_clr = 1'b0;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b0;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b0;
pc_prectl=PC_IGN;
- zz_is_nop = ZERO;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- if (id_cmd ==ID_NOI)
- NextState_Sreg0 = `NOI;
- else if (id_cmd==ID_CUR)
- NextState_Sreg0 = `CUR;
- else if (id_cmd==ID_MUL)
- NextState_Sreg0 = `MUL;
- else if (id_cmd==ID_LD)
- NextState_Sreg0 = `LD;
- else if (id_cmd==ID_RET)
- NextState_Sreg0 = `RET;
- else
- NextState_Sreg0 = `IDLE;
- end
- `D2_MUL_DLY:
- begin
- id2ra_ins_clr=ONE;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ONE;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr=ZERO;
- pc_prectl =PC_KEP;
- iack=riack;
- zz_is_nop = ONE;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- if (delay_counter_Sreg0 == 0)
- NextState_Sreg0 = `IDLE;
- else
- begin
- NextState_Sreg0 = `D2_MUL_DLY;
- // if (delay_counter_Sreg0 != 0)
- next_delay_counter_Sreg0 = delay_counter_Sreg0 - 1;
- end
- end
-
- default : //the same as RST
- begin
- id2ra_ins_clr=ONE;
- id2ra_ins_cls=ZERO;
- id2ra_ctl_clr=ONE;
- id2ra_ctl_cls=ZERO;
- ra2exec_ctl_clr=ONE;
+ zz_is_nop = 1'b0;end
+ default begin
+ id2ra_ins_clr = 1'b1;
+ id2ra_ins_cls = 1'b0;
+ id2ra_ctl_clr = 1'b1;
+ id2ra_ctl_cls = 1'b0;
+ ra2exec_ctl_clr = 1'b1;
pc_prectl=PC_RST;
- iack=ZERO;
- riack=ZERO;
- zz_is_nop = ONE;
- if (~rst)
- NextState_Sreg0 = `RST;
- else
- NextState_Sreg0 =`IDLE;
- end
-
+ zz_is_nop = 1'b1;end
endcase
end
-
- always @ (posedge clk)
- begin : Sreg0_CurrentState
- if (~rst)
- CurrState_Sreg0 <= `RST;
- else
- CurrState_Sreg0 <= NextState_Sreg0;
- end
-
- always @ (posedge clk )
- begin : Sreg0_RegOutput
- if (~rst)
- begin
- delay_counter_Sreg0 <=40; // Initialization in the reset state or default value required!!
- end
- else
- begin
- delay_counter_Sreg0 <= next_delay_counter_Sreg0;
- end
- end
endmodule
1.9 mips789/rtl/verilog/dvc.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/dvc.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: dvc.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/dvc.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- dvc.v 26 Nov 2007 13:46:21 -0000 1.8
+++ dvc.v 29 Nov 2007 03:50:36 -0000 1.9
@@ -22,17 +22,12 @@
output tmr_req,
output [31:0] cntr_o
);
-
reg [31:0]s_cntr;
reg [31:0]cntr;
-
assign cntr_o=cntr;
-
always @(posedge clk)
if (ld)
s_cntr<= din;
-
-
always @(posedge clk)
if (ld)
cntr<=din;
@@ -40,9 +35,7 @@
cntr<=s_cntr;
else if (tmr_en)
cntr<=cntr-1;
-
wire w_irq = cntr==0;
-
tmr_d itmr_d(
.clr(clr),
.clk(clk),
@@ -77,22 +70,22 @@
input [3:0] addr;
begin
case(addr)
- 0: seg = 7'b0111111;
- 1: seg = 7'b0000110;
- 2: seg = 7'b1011011;
- 3: seg = 7'b1001111;
- 4: seg = 7'b1100110;
- 5: seg = 7'b1101101;
- 6: seg = 7'b1111100;
- 7: seg = 7'b0000111;
- 8: seg = 7'b1111111;
- 9: seg = 7'b1100111;
- 10: seg = 7'b1110111;
- 11: seg = 7'b1111100;
- 12: seg = 7'b1011000;
- 13: seg = 7'b1011110;
- 14: seg = 7'b1111001;
- 15: seg = 7'b1110001;
+ 0: seg = 7'b011_1111;
+ 1: seg = 7'b000_0110;
+ 2: seg = 7'b101_1011;
+ 3: seg = 7'b100_1111;
+ 4: seg = 7'b110_0110;
+ 5: seg = 7'b110_1101;
+ 6: seg = 7'b111_1100;
+ 7: seg = 7'b000_0111;
+ 8: seg = 7'b111_1111;
+ 9: seg = 7'b110_0111;
+ 10: seg = 7'b111_0111;
+ 11: seg = 7'b111_1100;
+ 12: seg = 7'b101_1000;
+ 13: seg = 7'b101_1110;
+ 14: seg = 7'b111_1001;
+ 15: seg = 7'b111_0001;
default seg = 7'bx;
endcase
end
1.9 mips789/rtl/verilog/forward.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/forward.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: forward.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/forward.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- forward.v 26 Nov 2007 13:46:21 -0000 1.8
+++ forward.v 29 Nov 2007 03:50:36 -0000 1.9
@@ -46,8 +46,9 @@
case (fw_ctl)
`FW_ALU :dout=fw_alu;
`FW_MEM :dout=fw_dmem;
- `FW_NOP :dout=din;
- default dout=din;
+ default
+ /*`FW_NOP :dout=din;*/
+ dout=din;
endcase
endmodule
1.8 mips789/rtl/verilog/mem_module.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mem_module.v.diff?r1=1.7&r2=1.8
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mem_module.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mem_module.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- mem_module.v 18 Nov 2007 03:36:45 -0000 1.7
+++ mem_module.v 29 Nov 2007 03:50:36 -0000 1.8
@@ -99,6 +99,7 @@
wire [1:0]byte_addr_i;
assign byte_addr_i = dmem_addr_i[1:0] ;
+
always @(posedge clk)
begin
ctl_o<=(dmem_addr_i[31]==0)?ctl_i:0;
@@ -142,7 +143,6 @@
endmodule
-
module mem_dout_ctl(
input [1:0]byte_addr,
input [3:0]ctl,
@@ -150,41 +150,19 @@
output reg [31:0] dout
);
- wire [31:0] w31 = {
- din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31],
- din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31],
- din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31],
- din[31],din[31],din[31],din[31],din[31],din[31],din[31],din[31]} ;
-
- wire [31:0] w23 = {
- din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23],
- din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23],
- din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23],
- din[23],din[23],din[23],din[23],din[23],din[23],din[23],din[23]} ;
-
- wire [31:0] w15 = {
- din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15],
- din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15],
- din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15],
- din[15],din[15],din[15],din[15],din[15],din[15],din[15],din[15]} ;
- wire [31:0] w7 = {
- din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7],
- din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7],
- din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7],
- din[7],din[7],din[7],din[7],din[7],din[7],din[7],din[7]} ;
-
always @(*)
case (ctl)
`DMEM_LBS :
case (byte_addr)
- 'd0:dout={w31[23:0],din[31:24]};
- 'd1:dout={w23[23:0],din[23:16]};
- 'd2:dout={w15[23:0],din[15:8]};
- 'd3:dout={w7[23:0],din[7:0] };
+
+ 'd0:dout={{24{din[31]}},din[31:24]};
+ 'd1:dout={{24{din[23]}},din[23:16]};
+ 'd2:dout={{24{din[15]}},din[15:8]};
+ 'd3:dout={{24{din[7]}},din[7:0] };
default :
- dout=32'b0;
- endcase//checked
+ dout=32'bX;
+ endcase
`DMEM_LBU :
case (byte_addr)
'd3:dout={24'b0,din[7:0]};
@@ -192,19 +170,19 @@
'd1:dout={24'b0,din[23:16]};
'd0:dout={24'b0,din[31:24]};
default :
- dout=32'b0;
+ dout=32'bX;
endcase
`DMEM_LHU :
case (byte_addr)
'd0:dout={16'b0,din[31:24],din[23:16]};
'd2:dout={16'b0,din[15:8],din[7 :0]};
- default:dout=0;
+ default:dout=32'bX;
endcase
`DMEM_LHS :
case (byte_addr)
- 'd0 :dout={w31[15:0],din[31:24],din[23:16]};
- 'd2 :dout={w15[15:0],din[15:8],din[7 :0]};
- default:dout=0;
+ 'd0 :dout={{16{din[31]}},din[31:24],din[23:16]};
+ 'd2 :dout={{16{din[15]}},din[15:8],din[7 :0]};
+ default:dout=32'bX;
endcase
`DMEM_LW :
dout=din;
@@ -228,7 +206,7 @@
dout = {din[15:0],din[15:0]};
`DMEM_SW :
dout =din;
- default dout=din;
+ default dout=32'bX;
endcase
endmodule
1.5 mips789/rtl/verilog/mips789_defs.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips789_defs.v.diff?r1=1.4&r2=1.5
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips789_defs.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips789_defs.v,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- mips789_defs.v 26 Nov 2007 13:46:21 -0000 1.4
+++ mips789_defs.v 29 Nov 2007 03:50:36 -0000 1.5
@@ -179,6 +179,8 @@
`define COUNTER_VALUE2 (`COUNTER_VALUE1*2+1)
`define COUNTER_VALUE3 (`COUNTER_VALUE1+3)
+ `define DEFAULT_IRQ_ADDR 'H00_00_00_5C
+
`define ALTERA
`else
1.8 mips789/rtl/verilog/mips_uart.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/mips_uart.v.diff?r1=1.7&r2=1.8
(In the diff below, changes in quantity of whitespace are not shown.)
Index: mips_uart.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/mips_uart.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- mips_uart.v 18 Nov 2007 03:36:45 -0000 1.7
+++ mips_uart.v 29 Nov 2007 03:50:36 -0000 1.8
@@ -48,6 +48,20 @@
wire clk_uart=clk;
wire w_rxd_rdy;
+ integer uart_send;
+initial begin
+
+
+
+ uart_send = $fopen("uart_send.txt");
+
+
+end
+
+always @ (txd_ld)
+begin
+ if (txd_ld) $fwrite( uart_send,"%c",din[7:0]);
+end
uart_read uart_rd_tak(
.sync_reset(rst),
1.9 mips789/rtl/verilog/ulit.v
http://www.opencores.org/cvsweb.shtml/mips789/rtl/verilog/ulit.v.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: ulit.v
===================================================================
RCS file: /cvsroot/mcupro/mips789/rtl/verilog/ulit.v,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- ulit.v 26 Nov 2007 13:46:21 -0000 1.8
+++ ulit.v 29 Nov 2007 03:50:36 -0000 1.9
@@ -115,6 +115,7 @@
endmodule */
//these modules below are genated automaticly by a software written in C language...
+//Some of these may not be used
module ext_ctl_reg_clr_cls(input[`EXT_CTL_LEN-1:0] ext_ctl_i,output reg[`EXT_CTL_LEN-1:0] ext_ctl_o,input clk,input clr,input cls);always@(posedge clk)if(clr) ext_ctl_o<=0;else if(cls)ext_ctl_o<=ext_ctl_o;else ext_ctl_o<=ext_ctl_i;endmodule
module rd_sel_reg_clr_cls(input[`RD_SEL_LEN-1:0] rd_sel_i,output reg[`RD_SEL_LEN-1:0] rd_sel_o,input clk,input clr,input cls);always@(posedge clk)if(clr) rd_sel_o<=0;else if(cls)rd_sel_o<=rd_sel_o;else rd_sel_o<=rd_sel_i;endmodule
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