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From: cvs at opencores.org<cvs@o...>
Date: Fri Jun 1 19:13:33 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/07/06 01:19:13

Modified: jop/vhdl/scio scio_mikjen.vhd
Log:
no message


Revision Changes Path
1.2 jop/vhdl/scio/scio_mikjen.vhd

http://www.opencores.org/cvsweb.shtml/jop/vhdl/scio/scio_mikjen.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: scio_mikjen.vhd
===================================================================
RCS file: /cvsroot/9914pich/jop/vhdl/scio/scio_mikjen.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- scio_mikjen.vhd 17 Apr 2006 15:34:22 -0000 1.1
+++ scio_mikjen.vhd 1 Jun 2007 17:13:33 -0000 1.2
@@ -193,31 +193,29 @@

use work.jop_types.all;
use work.jop_config.all;
+use work.sc_pack.all;

entity scio is
-generic (addr_bits : integer);
-
port (
clk : in std_logic;
reset : in std_logic;

--- SimpCon interface
-
- address : in std_logic_vector(addr_bits-1 downto 0);
- wr_data : in std_logic_vector(31 downto 0);
- rd, wr : in std_logic;
- rd_data : out std_logic_vector(31 downto 0);
- rdy_cnt : out unsigned(1 downto 0);
-
--- interrupt
+--
+-- SimpCon IO interface
+--
+ sc_io_out : in sc_io_out_type;
+ sc_io_in : out sc_in_type;

- irq : out std_logic;
- irq_ena : out std_logic;
+--
+-- Interrupts from IO devices
+--
+ irq_in : out irq_in_type;
+ exc_req : in exception_type;

--- exception
+ -- CMP

- exc_req : in exception_type;
- exc_int : out std_logic;
+ sync_out : in sync_out_type := NO_SYNC;
+ sync_in : out sync_in_type;

-- serial interface

@@ -278,20 +276,20 @@

assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";

- sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));
+ sel <= to_integer(unsigned(sc_io_out.address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));

-- What happens when sel_reg > SLAVE_CNT-1??
- rd_data <= sc_dout(sel_reg);
+ sc_io_in.rd_data <= sc_dout(sel_reg);
-- rdy_cnt <= sc_rdy_cnt(sel_reg);
-rdy_cnt <= "00";
+ sc_io_in.rdy_cnt <= "00";

--
-- Connect SLAVE_CNT slaves
--
gsl: for i in 0 to SLAVE_CNT-1 generate

- sc_rd(i) <= rd when i=sel else '0';
- sc_wr(i) <= wr when i=sel else '0';
+ sc_rd(i) <= sc_io_out.rd when i=sel else '0';
+ sc_wr(i) <= sc_io_out.wr when i=sel else '0';

end generate;

@@ -303,32 +301,33 @@
if (reset='1') then
sel_reg <= 0;
elsif rising_edge(clk) then
- if rd='1' then
+ if sc_io_out.rd='1' then
sel_reg <= sel;
end if;
end if; end process; - cmp_cnt: entity work.sc_cnt generic map ( + cmp_sys: entity work.sc_sys generic map ( addr_bits => SLAVE_ADDR_BITS, - clk_freq => clk_freq + clk_freq => clk_freq, + cpu_id => 0 ) port map( clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(0), wr => sc_wr(0), rd_data => sc_dout(0), rdy_cnt => sc_rdy_cnt(0), - irq => irq, - irq_ena => irq_ena, - + irq_in => irq_in, exc_req => exc_req, - exc_int => exc_int, + + sync_out => sync_out, + sync_in => sync_in, wd => wd ); @@ -346,8 +345,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(1), wr => sc_wr(1), rd_data => sc_dout(1), @@ -403,8 +402,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(4), wr => sc_wr(4), rd_data => sc_dout(4), @@ -445,8 +444,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(5), wr => sc_wr(5), rd_data => sc_dout(5), @@ -473,8 +472,8 @@ clk => clk, reset => reset, - address => address(SLAVE_ADDR_BITS-1 downto 0), - wr_data => wr_data, + address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0), + wr_data => sc_io_out.wr_data, rd => sc_rd(6), wr => sc_wr(6), rd_data => sc_dout(6),