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From: cvs at opencores.org<cvs@o...>
Date: Wed May 30 07:25:56 CEST 2007
Subject: [cvs-checkins] MODIFIED: lq057q3dc02 ...
Date: 00/07/05 30:07:25

Modified: lq057q3dc02/hdl/vhsic/coe_image_gen clk_lcd_cyc_cntr.vhd
enab_control.vhd image_gen_bram.vhd
Log:
Comments.


Revision Changes Path
1.5 lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd.diff?r1=1.4&r2=1.5

(In the diff below, changes in quantity of whitespace are not shown.)

Index: clk_lcd_cyc_cntr.vhd
===================================================================
RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- clk_lcd_cyc_cntr.vhd 29 May 2007 19:45:13 -0000 1.4
+++ clk_lcd_cyc_cntr.vhd 30 May 2007 05:25:55 -0000 1.5
@@ -18,7 +18,7 @@
--
------------------------------------------------------------------------------
--
--- $Id: clk_lcd_cyc_cntr.vhd,v 1.4 2007/05/29 19:45:13 jwdonal Exp $
+-- $Id: clk_lcd_cyc_cntr.vhd,v 1.5 2007/05/30 05:25:55 jwdonal Exp $
--
-- Description:
-- Counts the number of CLK_LCD cycles that have occured after C_VSYNC_TVS
@@ -108,8 +108,8 @@
--////////////////////////--
ARCHITECTURE clk_lcd_cyc_cntr_arch OF clk_lcd_cyc_cntr IS

- constant C_NUM_LCD_LINES : positive := 240;
- constant C_NUM_LCD_PIXELS : positive := 320;
+ constant C_NUM_LCD_LINES : positive := 240; -- number of drawable lines in the LCD
+ constant C_NUM_LCD_PIXELS : positive := 320; -- number of drawable pixels per line in the LCD

--Enables/disables counter for pixel/enab counter process
signal clk_cyc_cnt_en_sig : std_logic := '0';



1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/enab_control.vhd

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/enab_control.vhd.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: enab_control.vhd
===================================================================
RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/enab_control.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- enab_control.vhd 29 May 2007 19:45:13 -0000 1.3
+++ enab_control.vhd 30 May 2007 05:25:55 -0000 1.4
@@ -18,7 +18,7 @@
--
------------------------------------------------------------------------------
--
--- $Id: enab_control.vhd,v 1.3 2007/05/29 19:45:13 jwdonal Exp $
+-- $Id: enab_control.vhd,v 1.4 2007/05/30 05:25:55 jwdonal Exp $
--
-- Description:
-- This file controls ENAB. This is the hardest state machine of the three. ENAB
@@ -80,6 +80,8 @@
generic (
C_VSYNC_TVS,

+ C_CLK_LCD_CYC_NUM_WIDTH,
+
C_ENAB_TEP,
C_ENAB_THE : POSITIVE
);
@@ -88,7 +90,7 @@
RSTx,
CLK_LCD : IN std_logic;

- CLK_LCD_CYC_NUM : IN std_logic_vector(9-1 downto 0);
+ CLK_LCD_CYC_NUM : IN std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0);

ENAB : OUT std_logic
);



1.5 lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd.diff?r1=1.4&r2=1.5

(In the diff below, changes in quantity of whitespace are not shown.)

Index: image_gen_bram.vhd
===================================================================
RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- image_gen_bram.vhd 29 May 2007 19:45:13 -0000 1.4 +++ image_gen_bram.vhd 30 May 2007 05:25:55 -0000 1.5 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: image_gen_bram.vhd,v 1.4 2007/05/29 19:45:13 jwdonal Exp $ +-- $Id: image_gen_bram.vhd,v 1.5 2007/05/30 05:25:55 jwdonal Exp $ -- -- Description: This file controls the BRAM components for each color. -- @@ -111,7 +111,7 @@ --////////////////////////-- ARCHITECTURE image_gen_bram_arch OF image_gen_bram IS - constant C_NUM_LCD_PIXELS : positive := 320; + constant C_NUM_LCD_PIXELS : positive := 320; -- number of drawable pixels per line in the LCD --Connecting signal wires between components signal SINIT_wire : std_logic := '0';