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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue May 29 21:45:14 CEST 2007
    Subject: [cvs-checkins] MODIFIED: lq057q3dc02 ...
    Top
    Date: 00/07/05 29:21:45

    Modified: lq057q3dc02/hdl/vhsic/coe_image_gen clk_lcd_cyc_cntr.vhd
    components.vhd enab_control.vhd hsyncx_control.vhd
    image_gen_bram.vhd lq057q3dc02.vhd
    lq057q3dc02_tb.vhd modelsim_wave.do
    video_controller.vhd vsyncx_control.vhd
    Log:
    Added more generics and timespec assert constraints.


    Revision Changes Path
    1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd

    http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd.diff?r1=1.3&r2=1.4

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: clk_lcd_cyc_cntr.vhd
    ===================================================================
    RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd,v
    retrieving revision 1.3
    retrieving revision 1.4
    diff -u -b -r1.3 -r1.4
    --- clk_lcd_cyc_cntr.vhd 29 May 2007 09:16:48 -0000 1.3
    +++ clk_lcd_cyc_cntr.vhd 29 May 2007 19:45:13 -0000 1.4
    @@ -18,7 +18,7 @@
    --
    ------------------------------------------------------------------------------
    --
    --- $Id: clk_lcd_cyc_cntr.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $
    +-- $Id: clk_lcd_cyc_cntr.vhd,v 1.4 2007/05/29 19:45:13 jwdonal Exp $
    --
    -- Description:
    -- Counts the number of CLK_LCD cycles that have occured after C_VSYNC_TVS
    @@ -80,6 +80,9 @@

    generic (
    C_VSYNC_TVS,
    + C_LINE_NUM_WIDTH,
    +
    + C_CLK_LCD_CYC_NUM_WIDTH,

    C_ENAB_TEP,
    C_ENAB_THE : POSITIVE
    @@ -92,9 +95,9 @@
    HSYNCx,
    VSYNCx : IN std_logic;

    - LINE_NUM : IN std_logic_vector(9-1 downto 0);
    + LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0);

    - CLK_LCD_CYC_NUM : OUT std_logic_vector(9-1 downto 0)
    + CLK_LCD_CYC_NUM : OUT std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0)

    );

    @@ -109,10 +112,10 @@
    constant C_NUM_LCD_PIXELS : positive := 320;

    --Enables/disables counter for pixel/enab counter process
    - signal clk_cyc_cnt_en_sig : std_logic;
    + signal clk_cyc_cnt_en_sig : std_logic := '0';

    --Stores the number of CLK_LCD cycles that have occurred
    - signal clk_cyc_num_reg : std_logic_vector(8 downto 0);
    + signal clk_cyc_num_reg : std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) := (others => '0');

    ---------------------------------------------------------------
    -- States for CLK_Cntr_cntrl_*_PROC
    @@ -247,9 +250,9 @@

    end if;

    - when ACTIVE => -- Now that ENAB is active we want it to stay active for TEP CLK_LCD cycles (i.e. 320 pixels)
    + when ACTIVE => -- Now that ENAB is active we want it to stay active for TEP CLK_LCD cycles

    - if( clk_cyc_num_reg = C_ENAB_THE + C_NUM_LCD_PIXELS - 1 ) then -- C_ENAB_THE to C_ENAB_THE + (320 - 1) = 320 clocks!
    + if( clk_cyc_num_reg = C_ENAB_THE + C_NUM_LCD_PIXELS - 1 ) then -- C_ENAB_THE to C_ENAB_THE + (320 - 1) = C_ENAB_TEP clocks!

    CLK_Cntr_ns <= INACTIVE_WAIT_1; -- once TEP clocks have passed we disable ENAB!




    1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/components.vhd

    http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/components.vhd.diff?r1=1.3&r2=1.4

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: components.vhd
    ===================================================================
    RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/components.vhd,v
    retrieving revision 1.3
    retrieving revision 1.4
    diff -u -b -r1.3 -r1.4
    --- components.vhd 29 May 2007 09:16:48 -0000 1.3
    +++ components.vhd 29 May 2007 19:45:13 -0000 1.4
    @@ -18,7 +18,7 @@
    --
    ------------------------------------------------------------------------------
    -- --- $Id: components.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $ +-- $Id: components.vhd,v 1.4 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: -- This is a package that lists all of the components used in the design. @@ -91,6 +91,9 @@ COMPONENT clk_lcd_cyc_cntr is GENERIC ( C_VSYNC_TVS, + C_LINE_NUM_WIDTH, + + C_CLK_LCD_CYC_NUM_WIDTH, C_ENAB_TEP, C_ENAB_THE : POSITIVE @@ -102,9 +105,9 @@ HSYNCx, VSYNCx : IN std_logic; - LINE_NUM : IN std_logic_vector(9-1 downto 0); + LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0); - CLK_LCD_CYC_NUM : OUT std_logic_vector(9-1 downto 0) + CLK_LCD_CYC_NUM : OUT std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) ); END COMPONENT clk_lcd_cyc_cntr; @@ -122,12 +125,17 @@ C_VSYNC_TV, C_VSYNC_TVP, C_VSYNC_TVS, + C_LINE_NUM_WIDTH, --HSYNCx Controller (pass thru) C_HSYNC_TH, C_HSYNC_THP, + C_NUM_CLKS_WIDTH, + + --CLK_LCD Cycle Counter (pass thru) + C_CLK_LCD_CYC_NUM_WIDTH, - --ENAB Controller + --ENAB Controller (pass thru) C_ENAB_TEP, C_ENAB_THE : POSITIVE ); @@ -136,9 +144,9 @@ RSTx, CLK_LCD : IN STD_LOGIC; - LINE_NUM : OUT STD_LOGIC_VECTOR(9-1 downto 0); + LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0); - CLK_LCD_CYC_NUM : OUT STD_LOGIC_VECTOR(9-1 downto 0); + CLK_LCD_CYC_NUM : OUT STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0); HSYNCx, VSYNCx, @@ -156,7 +164,8 @@ COMPONENT hsyncx_control is GENERIC ( C_HSYNC_TH, - C_HSYNC_THP : POSITIVE + C_HSYNC_THP, + C_NUM_CLKS_WIDTH : POSITIVE ); PORT ( RSTx, @@ -173,7 +182,8 @@ COMPONENT vsyncx_control is GENERIC ( C_VSYNC_TV, - C_VSYNC_TVP : POSITIVE + C_VSYNC_TVP, + C_LINE_NUM_WIDTH : POSITIVE ); PORT ( @@ -181,7 +191,7 @@ CLK_LCD, HSYNCx : IN STD_LOGIC; - LINE_NUM : OUT STD_LOGIC_VECTOR(9-1 downto 0); + LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0); VSYNCx : OUT STD_LOGIC ); @@ -195,6 +205,8 @@ GENERIC ( C_VSYNC_TVS, + C_CLK_LCD_CYC_NUM_WIDTH, + C_ENAB_TEP, C_ENAB_THE : POSITIVE ); @@ -202,7 +214,7 @@ RSTx, CLK_LCD : IN STD_LOGIC; - CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(9-1 downto 0); + CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0); ENAB : OUT STD_LOGIC ); @@ -217,6 +229,9 @@ C_BIT_DEPTH, C_VSYNC_TVS, + C_LINE_NUM_WIDTH, + + C_CLK_LCD_CYC_NUM_WIDTH, C_ENAB_TEP, C_ENAB_THE, @@ -229,9 +244,9 @@ RSTx, CLK_LCD : IN STD_LOGIC; - LINE_NUM : IN STD_LOGIC_VECTOR(9-1 downto 0); + LINE_NUM : IN STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0); - CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(9-1 downto 0); + CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0); R, G, 1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/enab_control.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/enab_control.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: enab_control.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/enab_control.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- enab_control.vhd 29 May 2007 08:13:57 -0000 1.2 +++ enab_control.vhd 29 May 2007 19:45:13 -0000 1.3 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: enab_control.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $ +-- $Id: enab_control.vhd,v 1.3 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: -- This file controls ENAB. This is the hardest state machine of the three. ENAB @@ -88,7 +88,7 @@ RSTx, CLK_LCD : IN std_logic; - CLK_LCD_CYC_NUM : IN std_logic_vector(8 downto 0); + CLK_LCD_CYC_NUM : IN std_logic_vector(9-1 downto 0); ENAB : OUT std_logic ); 1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/hsyncx_control.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/hsyncx_control.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: hsyncx_control.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/hsyncx_control.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- hsyncx_control.vhd 29 May 2007 08:13:57 -0000 1.2 +++ hsyncx_control.vhd 29 May 2007 19:45:13 -0000 1.3 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: hsyncx_control.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $ +-- $Id: hsyncx_control.vhd,v 1.3 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: -- This file controls the HSYNCx signal. The HSYNCx state machine is @@ -86,7 +86,8 @@ generic ( C_HSYNC_TH, - C_HSYNC_THP : POSITIVE + C_HSYNC_THP, + C_NUM_CLKS_WIDTH : POSITIVE ); port ( @@ -103,16 +104,14 @@ --////////////////////////-- ARCHITECTURE hsyncx_control_arch OF hsyncx_control IS - -- Number of clock cycles that have occurred - -- (need at least 9 bits to hold value of max TH value of 450) - signal num_hsyncx_clocks_reg : std_logic_vector(8 downto 0) := "000000000"; + signal num_hsyncx_clks_reg : std_logic_vector(C_NUM_CLKS_WIDTH-1 downto 0) := (others => '0'); begin ------------------------------------------------------------------ -- Process Description: -- This process enables or disables the HSYNCx port depending - -- upon the number of clocks that have passed (num_hsyncx_clocks_reg) + -- upon the number of clocks that have passed (num_hsyncx_clks_reg) -- relative to C_HSYNC_THP. -- -- Inputs: @@ -134,7 +133,7 @@ elsif( CLK_LCD'event and CLK_LCD = '1' ) then - if( num_hsyncx_clocks_reg < C_HSYNC_THP ) then + if( num_hsyncx_clks_reg < C_HSYNC_THP ) then HSYNCx <= '0'; @@ -151,7 +150,7 @@ ------------------------------------------------------------------ -- Process Description: - -- This process controls the num_hsyncx_clocks_reg counter + -- This process controls the num_hsyncx_clks_reg counter -- and resets it when it has reached the defined C_HSYNC_TH -- parameter. -- @@ -160,7 +159,7 @@ -- CLK_LCD -- -- Outputs: - -- num_hsyncx_clocks_reg + -- num_hsyncx_clks_reg -- -- Notes: -- N/A @@ -170,17 +169,17 @@ if( RSTx = '0' ) then - num_hsyncx_clocks_reg <= (others => '0'); + num_hsyncx_clks_reg <= (others => '0'); elsif( CLK_LCD'event and CLK_LCD = '1' ) then - if( num_hsyncx_clocks_reg = C_HSYNC_TH - 1 ) then -- 0 to (TH - 1) = TH clocks! + if( num_hsyncx_clks_reg = C_HSYNC_TH - 1 ) then -- 0 to (TH - 1) = TH clocks! - num_hsyncx_clocks_reg <= (others => '0'); -- a full HSYNC cycle has completed. START OVER! + num_hsyncx_clks_reg <= (others => '0'); -- a full HSYNC cycle has completed. START OVER! else - num_hsyncx_clocks_reg <= num_hsyncx_clocks_reg + 1; -- keep counting until we have reached a full HSYNC cycle + num_hsyncx_clks_reg <= num_hsyncx_clks_reg + 1; -- keep counting until we have reached a full HSYNC cycle end if; 1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: image_gen_bram.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- image_gen_bram.vhd 29 May 2007 09:16:48 -0000 1.3 +++ image_gen_bram.vhd 29 May 2007 19:45:13 -0000 1.4 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: image_gen_bram.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $ +-- $Id: image_gen_bram.vhd,v 1.4 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: This file controls the BRAM components for each color. -- @@ -78,6 +78,9 @@ C_BIT_DEPTH, C_VSYNC_TVS, + C_LINE_NUM_WIDTH, + + C_CLK_LCD_CYC_NUM_WIDTH, C_ENAB_TEP, C_ENAB_THE, @@ -92,9 +95,9 @@ RSTx, CLK_LCD : IN std_logic; - LINE_NUM : IN std_logic_vector(9-1 downto 0); + LINE_NUM : IN std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0); - CLK_LCD_CYC_NUM : IN std_logic_vector(9-1 downto 0); + CLK_LCD_CYC_NUM : IN std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0); R, G, @@ -111,8 +114,8 @@ constant C_NUM_LCD_PIXELS : positive := 320; --Connecting signal wires between components - signal SINIT_wire : std_logic; - signal ADDR_wire : std_logic_vector(C_BRAM_ADDR_WIDTH-1 downto 0); + signal SINIT_wire : std_logic := '0'; + signal ADDR_wire : std_logic_vector(C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0'); begin 1.7 lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd.diff?r1=1.6&r2=1.7 (In the diff below, changes in quantity of whitespace are not shown.) Index: lq057q3dc02.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd,v retrieving revision 1.6 retrieving revision 1.7 diff -u -b -r1.6 -r1.7 --- lq057q3dc02.vhd 29 May 2007 09:16:48 -0000 1.6 +++ lq057q3dc02.vhd 29 May 2007 19:45:13 -0000 1.7 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: lq057q3dc02.vhd,v 1.6 2007/05/29 09:16:48 jwdonal Exp $ +-- $Id: lq057q3dc02.vhd,v 1.7 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: -- Top level file for the lq057q3dc02 pcore. The lq057q3dc02 supports QVGA @@ -108,28 +108,42 @@ -- -- C_BIT_DEPTH -- Bit depth of this LCD -- - -- Video Controller (pass thru) + -- Video Controller (passed thru from top-level to component) -- C_RL_STATUS -- Value to use for the RL port -- C_UD_STATUS -- Value to use for the UD port -- C_VQ_STATUS -- Value to use for the VQ port -- - -- VSYNCx Controller (pass thru) + -- VSYNCx Controller (passed thru from top-level to component) -- C_VSYNC_TV -- VSYNCx cycle time (in lines) -- C_VSYNC_TVP -- VSYNCx pulse width (in lines) -- C_VSYNC_TVS -- VSYNCx start position (in lines) - We can't start -- -- sending data until at least 7 lines have passed -- -- (i.e. start sending data on the 8th line). + -- C_LINE_NUM_WIDTH -- Width of register that stores current line number + -- -- (need at least 9 bits to hold maximum TV + -- -- timespec value of 280) -- - -- HSYNCx Controller (pass thru) + -- HSYNCx Controller (passed thru from top-level to component) -- C_HSYNC_TH -- HSYNCx cycle time (in clocks) -- C_HSYNC_THP -- HSYNCx pulse width (in clocks) (maximum pulse width is -- -- best b/c it will conserver the most power) + -- C_NUM_CLKS_WIDTH -- Width of register that stores current number of + -- -- clock cycles that have occurred. + -- -- (need at least 9 bits to hold maximum TH + -- -- timespec value of 450) -- - -- ENAB Controller (pass thru) + -- CLK_LCD Cycle Counter (passed thru from top-level to component) + -- C_CLK_LCD_CYC_NUM_WIDTH -- Width of register that stores current number + -- -- of clock cycles that have occurred. + -- -- (need at least 9 bits to hold maximum timespec + -- -- value of full screen image width (320 clocks) + -- -- + maximum timespec value of C_ENAB_THE + -- -- ([C_ENAB_TH_max - 340] clocks) = 430) + -- ENAB Controller (passed thru from top-level to component) -- C_ENAB_TEP -- ENAB pulse width (in clocks) -- C_ENAB_THE -- HSYNCx-ENAB phase difference (in clocks) -- - -- Image Generator (pass thru) + -- Image Generator (passed thru from top-level to component) -- Change these when changing the image -- Also, cleanup all project files, and delete all auto-generated -- image_gen_bram files. @@ -150,9 +164,13 @@ C_VSYNC_TV : POSITIVE := 255; C_VSYNC_TVP : POSITIVE := 3; C_VSYNC_TVS : POSITIVE := 7; + C_LINE_NUM_WIDTH : POSITIVE := 9; C_HSYNC_TH : POSITIVE := 400; C_HSYNC_THP : POSITIVE := 10; + C_NUM_CLKS_WIDTH : POSITIVE := 9; + + C_CLK_LCD_CYC_NUM_WIDTH : POSITIVE := 9; C_ENAB_TEP : POSITIVE := 320; C_ENAB_THE : POSITIVE := 8; @@ -213,11 +231,11 @@ ARCHITECTURE lq057q3dc02_arch OF lq057q3dc02 IS --Connecting wires to carry signals b/w components - signal CLK_LCD_wire : std_logic; - signal HSYNCx_wire : std_logic; - signal VSYNCx_wire : std_logic; - signal LINE_NUM_wire : std_logic_vector(9-1 downto 0); - signal CLK_LCD_CYC_NUM_wire : std_logic_vector(9-1 downto 0); + signal CLK_LCD_wire : std_logic := '0'; + signal HSYNCx_wire : std_logic := '1'; + signal VSYNCx_wire : std_logic := '1'; + signal LINE_NUM_wire : std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0) := (others => '0'); + signal CLK_LCD_CYC_NUM_wire : std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) := (others => '0'); begin @@ -242,6 +260,10 @@ REPORT "ERROR - lq057q3dc02: Invalid value for generic C_VSYNC_TVS (must be 7)" SEVERITY FAILURE; + ASSERT C_LINE_NUM_WIDTH = 9 + REPORT "ERROR - lq057q3dc02: Invalid value for generic C_LINE_NUM_WIDTH (must be 9 to hold maximum TV timespec value of 280" + SEVERITY FAILURE; + ASSERT C_HSYNC_TH >= 360 and C_HSYNC_TH <= 450 REPORT "ERROR - lq057q3dc02: Invalid value for generic C_HSYNC_TH (must be >= 360 and <= 450)" SEVERITY FAILURE; @@ -250,6 +272,14 @@ REPORT "ERROR - lq057q3dc02: Invalid value for generic C_HSYNC_THP (must be >= 2 and <= 200)" SEVERITY FAILURE; + ASSERT C_NUM_CLKS_WIDTH = 9 + REPORT "ERROR - lq057q3dc02: Invalid value for generic C_NUM_CLKS_WIDTH (must be 9 to hold maximum TH timespec value of 450" + SEVERITY FAILURE; + + ASSERT C_CLK_LCD_CYC_NUM_WIDTH = 9 + REPORT "ERROR - lq057q3dc02: Invalid value for generic C_CLK_LCD_CYC_NUM_WIDTH (must be 9 to hold maximum TH timespec value of 430" + SEVERITY FAILURE; + ASSERT C_ENAB_TEP >= 2 and C_ENAB_TEP <= (C_HSYNC_TH - 10) REPORT "ERROR - lq057q3dc02: Invalid value for generic C_ENAB_TEP (must be >= 2 and <= (C_HSYNC_TH - 10))" SEVERITY FAILURE; @@ -296,10 +326,15 @@ C_VSYNC_TV => C_VSYNC_TV, C_VSYNC_TVP => C_VSYNC_TVP, C_VSYNC_TVS => C_VSYNC_TVS, + C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH, --HSYNCx Controller C_HSYNC_TH => C_HSYNC_TH, C_HSYNC_THP => C_HSYNC_THP, + C_NUM_CLKS_WIDTH => C_NUM_CLKS_WIDTH, + + --CLK_LCD Cycle Counter + C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH, --ENAB Controller C_ENAB_TEP => C_ENAB_TEP, @@ -324,7 +359,12 @@ IMAGE : image_gen_bram GENERIC MAP ( C_BIT_DEPTH => C_BIT_DEPTH, + C_VSYNC_TVS => C_VSYNC_TVS, + C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH, + + C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH, + C_ENAB_TEP => C_ENAB_TEP, C_ENAB_THE => C_ENAB_THE, 1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02_tb.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02_tb.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: lq057q3dc02_tb.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02_tb.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- lq057q3dc02_tb.vhd 29 May 2007 08:13:57 -0000 1.2 +++ lq057q3dc02_tb.vhd 29 May 2007 19:45:13 -0000 1.3 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: lq057q3dc02_tb.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $ +-- $Id: lq057q3dc02_tb.vhd,v 1.3 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: -- Test bench to verify lq057q3dc02 pcore. @@ -89,7 +89,7 @@ R, G, - B : OUT std_logic_vector(5 downto 0) + B : OUT std_logic_vector(6-1 downto 0) ); END COMPONENT; @@ -112,7 +112,7 @@ signal R, G, - B : std_logic_vector(5 downto 0) := "UUUUUU"; + B : std_logic_vector(6-1 downto 0) := (others => 'U'); signal verifyDone : std_logic := '0'; 1.2 lq057q3dc02/hdl/vhsic/coe_image_gen/modelsim_wave.do http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/modelsim_wave.do.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: modelsim_wave.do =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/modelsim_wave.do,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- modelsim_wave.do 25 May 2007 11:20:02 -0000 1.1 +++ modelsim_wave.do 29 May 2007 19:45:13 -0000 1.2 @@ -8,12 +8,12 @@ add wave -noupdate -format Logic /lq057q3dc02_tb/vsyncx add wave -noupdate -divider -height 25 HSYNCx_Controller add wave -noupdate -format Logic /lq057q3dc02_tb/hsyncx -add wave -noupdate -format Literal -radix unsigned /lq057q3dc02_tb/uut/v_c/hsyncx_c/num_hsyncx_clocks +add wave -noupdate -format Literal -radix unsigned /lq057q3dc02_tb/uut/v_c/hsyncx_c/num_hsyncx_clocks_reg add wave -noupdate -divider -height 30 ENAB_Controller add wave -noupdate -format Logic /lq057q3dc02_tb/uut/v_c/enab_c/enab -add wave -noupdate -divider -height 30 P_E_Counter -add wave -noupdate -format Literal -radix unsigned /lq057q3dc02_tb/uut/v_c/p_e_cntr/p_e_clk_num -add wave -noupdate -format Literal /lq057q3dc02_tb/uut/v_c/p_e_cntr/p_e_cntr_curr_st +add wave -noupdate -divider -height 30 CLK_LCD_CYC_Counter +add wave -noupdate -format Literal -radix unsigned /lq057q3dc02_tb/uut/v_c/clk_lcd_cycle_cntr/clk_lcd_cyc_num +add wave -noupdate -format Literal /lq057q3dc02_tb/uut/v_c/clk_lcd_cycle_cntr/clk_cntr_cs add wave -noupdate -divider -height 30 Image_Gen add wave -noupdate -format Logic /lq057q3dc02_tb/uut/image/sinit_wire add wave -noupdate -format Literal -radix unsigned /lq057q3dc02_tb/uut/image/addr_wire @@ -22,7 +22,7 @@ add wave -noupdate -format Literal /lq057q3dc02_tb/g add wave -noupdate -format Literal /lq057q3dc02_tb/b TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {15799505000 ps} 0} +WaveRestoreCursors {{Cursor 1} {3024646983 ps} 0} configure wave -namecolwidth 361 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -36,4 +36,4 @@ configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {15798415982 ps} {15800791221 ps} +WaveRestoreZoom {887271898 ps} {887629557 ps} 1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/video_controller.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/video_controller.vhd.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: video_controller.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/video_controller.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- video_controller.vhd 29 May 2007 09:16:48 -0000 1.3 +++ video_controller.vhd 29 May 2007 19:45:13 -0000 1.4 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: video_controller.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $ +-- $Id: video_controller.vhd,v 1.4 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: -- This file instantiates the components which control HSYNCx, VSYNCx, ENAB, @@ -86,10 +86,15 @@ C_VSYNC_TV, C_VSYNC_TVP, C_VSYNC_TVS, + C_LINE_NUM_WIDTH, --HSYNCx Controller (pass thru) C_HSYNC_TH, C_HSYNC_THP, + C_NUM_CLKS_WIDTH, + + --CLK_LCD Cycle Counter (pass thru) + C_CLK_LCD_CYC_NUM_WIDTH, --ENAB Controller (pass thru) C_ENAB_TEP, @@ -100,17 +105,16 @@ RSTx, CLK_LCD : IN std_logic; - LINE_NUM : OUT std_logic_vector(9-1 downto 0); + LINE_NUM : OUT std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0); - CLK_LCD_CYC_NUM : OUT std_logic_vector(9-1 downto 0); + CLK_LCD_CYC_NUM : OUT std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0); HSYNCx, VSYNCx, ENAB, - RL, -- never changed in this code - UD, -- never changed in this code - VQ --:= '0'; -- alwasys 0 b/c VGA mode is not possible on this LCD! (QVGA only!) - : OUT std_logic + RL, + UD, + VQ : OUT std_logic ); END ENTITY video_controller; @@ -121,10 +125,10 @@ ARCHITECTURE video_controller_arch OF video_controller IS --Connecting wires between components - signal HSYNCx_wire : std_logic; - signal VSYNCx_wire : std_logic; - signal LINE_NUM_wire : std_logic_vector(9-1 downto 0); - signal CLK_LCD_CYC_NUM_wire : std_logic_vector(9-1 downto 0); + signal HSYNCx_wire : std_logic := '1'; + signal VSYNCx_wire : std_logic := '1'; + signal LINE_NUM_wire : std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0) := (others => '0'); + signal CLK_LCD_CYC_NUM_wire : std_logic_vector(C_CLK_LCD_CYC_NUM_WIDTH-1 downto 0) := (others => '0'); begin @@ -149,7 +153,8 @@ HSYNCx_C : hsyncx_control generic map ( C_HSYNC_TH => C_HSYNC_TH, - C_HSYNC_THP => C_HSYNC_THP + C_HSYNC_THP => C_HSYNC_THP, + C_NUM_CLKS_WIDTH => C_NUM_CLKS_WIDTH ) port map ( RSTx => RSTx, @@ -166,7 +171,8 @@ VSYNCx_C : vsyncx_control generic map ( C_VSYNC_TV => C_VSYNC_TV, - C_VSYNC_TVP => C_VSYNC_TVP + C_VSYNC_TVP => C_VSYNC_TVP, + C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH ) port map ( RSTx => RSTx, @@ -184,6 +190,10 @@ CLK_LCD_CYCLE_Cntr : clk_lcd_cyc_cntr GENERIC MAP ( C_VSYNC_TVS => C_VSYNC_TVS, + C_LINE_NUM_WIDTH => C_LINE_NUM_WIDTH, + + C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH, + C_ENAB_TEP => C_ENAB_TEP, C_ENAB_THE => C_ENAB_THE ) @@ -204,6 +214,9 @@ ENAB_C : enab_control generic map ( C_VSYNC_TVS => C_VSYNC_TVS, + + C_CLK_LCD_CYC_NUM_WIDTH => C_CLK_LCD_CYC_NUM_WIDTH, + C_ENAB_TEP => C_ENAB_TEP, C_ENAB_THE => C_ENAB_THE ) 1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/vsyncx_control.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/vsyncx_control.vhd.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: vsyncx_control.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/vsyncx_control.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- vsyncx_control.vhd 29 May 2007 09:16:48 -0000 1.3 +++ vsyncx_control.vhd 29 May 2007 19:45:13 -0000 1.4 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: vsyncx_control.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $ +-- $Id: vsyncx_control.vhd,v 1.4 2007/05/29 19:45:13 jwdonal Exp $ -- -- Description: -- This file controls VSYNCx. VSYNCx is dependent upon the number of HSYNCx @@ -101,9 +101,8 @@ generic ( C_VSYNC_TV, - C_VSYNC_TVP : POSITIVE; - - C_LINE_NUM_WIDTH : POSITIVE := 9 + C_VSYNC_TVP, + C_LINE_NUM_WIDTH : POSITIVE );

     
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