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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue May 29 11:16:48 CEST 2007
    Subject: [cvs-checkins] MODIFIED: lq057q3dc02 ...
    Top
    Date: 00/07/05 29:11:16

    Modified: lq057q3dc02/hdl/vhsic/coe_image_gen clk_lcd_cyc_cntr.vhd
    components.vhd image_gen_bram.vhd lq057q3dc02.tcl
    lq057q3dc02.vhd video_controller.vhd
    vsyncx_control.vhd
    Log:
    Changed width of LINE_NUM register to accept maximum possible timespec value for VSYNCx cycle time "TV".


    Revision Changes Path
    1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd

    http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd.diff?r1=1.2&r2=1.3

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: clk_lcd_cyc_cntr.vhd
    ===================================================================
    RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/clk_lcd_cyc_cntr.vhd,v
    retrieving revision 1.2
    retrieving revision 1.3
    diff -u -b -r1.2 -r1.3
    --- clk_lcd_cyc_cntr.vhd 29 May 2007 08:13:57 -0000 1.2
    +++ clk_lcd_cyc_cntr.vhd 29 May 2007 09:16:48 -0000 1.3
    @@ -18,7 +18,7 @@
    --
    ------------------------------------------------------------------------------
    --
    --- $Id: clk_lcd_cyc_cntr.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $
    +-- $Id: clk_lcd_cyc_cntr.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $
    --
    -- Description:
    -- Counts the number of CLK_LCD cycles that have occured after C_VSYNC_TVS
    @@ -92,9 +92,9 @@
    HSYNCx,
    VSYNCx : IN std_logic;

    - LINE_NUM : IN std_logic_vector(7 downto 0);
    + LINE_NUM : IN std_logic_vector(9-1 downto 0);

    - CLK_LCD_CYC_NUM : OUT std_logic_vector(8 downto 0)
    + CLK_LCD_CYC_NUM : OUT std_logic_vector(9-1 downto 0)

    );




    1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/components.vhd

    http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/components.vhd.diff?r1=1.2&r2=1.3

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: components.vhd
    ===================================================================
    RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/components.vhd,v
    retrieving revision 1.2
    retrieving revision 1.3
    diff -u -b -r1.2 -r1.3
    --- components.vhd 29 May 2007 08:13:57 -0000 1.2
    +++ components.vhd 29 May 2007 09:16:48 -0000 1.3
    @@ -18,7 +18,7 @@
    --
    ------------------------------------------------------------------------------
    --
    --- $Id: components.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $
    +-- $Id: components.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $
    --
    -- Description:
    -- This is a package that lists all of the components used in the design.
    @@ -102,9 +102,9 @@
    HSYNCx,
    VSYNCx : IN std_logic;

    - LINE_NUM : IN std_logic_vector(7 downto 0);
    + LINE_NUM : IN std_logic_vector(9-1 downto 0);

    - CLK_LCD_CYC_NUM : OUT std_logic_vector(8 downto 0)
    + CLK_LCD_CYC_NUM : OUT std_logic_vector(9-1 downto 0)
    );
    END COMPONENT clk_lcd_cyc_cntr;

    @@ -136,9 +136,9 @@
    RSTx,
    CLK_LCD : IN STD_LOGIC;

    - LINE_NUM : OUT STD_LOGIC_VECTOR(7 downto 0);
    + LINE_NUM : OUT STD_LOGIC_VECTOR(9-1 downto 0);

    - CLK_LCD_CYC_NUM : OUT STD_LOGIC_VECTOR(8 downto 0);
    + CLK_LCD_CYC_NUM : OUT STD_LOGIC_VECTOR(9-1 downto 0);

    HSYNCx,
    VSYNCx,
    @@ -181,7 +181,7 @@
    CLK_LCD,
    HSYNCx : IN STD_LOGIC;

    - LINE_NUM : OUT STD_LOGIC_VECTOR(7 downto 0);
    + LINE_NUM : OUT STD_LOGIC_VECTOR(9-1 downto 0);
    VSYNCx : OUT STD_LOGIC ); @@ -202,7 +202,7 @@ RSTx, CLK_LCD : IN STD_LOGIC; - CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(8 downto 0); + CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(9-1 downto 0); ENAB : OUT STD_LOGIC ); @@ -229,9 +229,9 @@ RSTx, CLK_LCD : IN STD_LOGIC; - LINE_NUM : IN STD_LOGIC_VECTOR(7 downto 0); + LINE_NUM : IN STD_LOGIC_VECTOR(9-1 downto 0); - CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(8 downto 0); + CLK_LCD_CYC_NUM : IN STD_LOGIC_VECTOR(9-1 downto 0); R, G, 1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: image_gen_bram.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- image_gen_bram.vhd 29 May 2007 08:13:57 -0000 1.2 +++ image_gen_bram.vhd 29 May 2007 09:16:48 -0000 1.3 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: image_gen_bram.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $ +-- $Id: image_gen_bram.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $ -- -- Description: This file controls the BRAM components for each color. -- @@ -92,9 +92,9 @@ RSTx, CLK_LCD : IN std_logic; - LINE_NUM : IN std_logic_vector(7 downto 0); + LINE_NUM : IN std_logic_vector(9-1 downto 0); - CLK_LCD_CYC_NUM : IN std_logic_vector(8 downto 0); + CLK_LCD_CYC_NUM : IN std_logic_vector(9-1 downto 0); R, G, 1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.tcl http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.tcl.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: lq057q3dc02.tcl =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.tcl,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- lq057q3dc02.tcl 25 May 2007 18:43:36 -0000 1.3 +++ lq057q3dc02.tcl 29 May 2007 09:16:48 -0000 1.4 @@ -1,4 +1,45 @@ -# Tcl script to run in the Xilinx Tcl shell or the ISE Tcl Console +############################################################################## +# Copyright (C) 2007 Jonathon W. Donaldson +# jwdonal a t opencores DOT org +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +############################################################################## +# +# $Id: lq057q3dc02.tcl,v 1.4 2007/05/29 09:16:48 jwdonal Exp $ +# +# Description: +# Tcl script to run in the Xilinx Tcl shell or the ISE Tcl Console. +# +# Structure: +# - xupv2p.ucf +# - components.vhd +# - lq057q3dc02_tb.vhd +# - lq057q3dc02.vhd +# - dcm_sys_to_lcd.xaw +# - video_controller.vhd +# - enab_control.vhd +# - hsyncx_control.vhd +# - vsyncx_control.vhd +# - clk_lcd_cyc_cntr.vhd +# - image_gen_bram.vhd +# - image_gen_bram_red.xco +# - image_gen_bram_green.xco +# - image_gen_bram_blue.xco +# +############################################################################## # To run this script, `cd' to the directory containg this file # using the Tcl shell/console. Type "source <filename>" at Tcl prompt. 1.6 lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd.diff?r1=1.5&r2=1.6 (In the diff below, changes in quantity of whitespace are not shown.) Index: lq057q3dc02.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd,v retrieving revision 1.5 retrieving revision 1.6 diff -u -b -r1.5 -r1.6 --- lq057q3dc02.vhd 29 May 2007 08:13:57 -0000 1.5 +++ lq057q3dc02.vhd 29 May 2007 09:16:48 -0000 1.6 @@ -18,15 +18,41 @@ -- ------------------------------------------------------------------------------ -- --- $Id: lq057q3dc02.vhd,v 1.5 2007/05/29 08:13:57 jwdonal Exp $ +-- $Id: lq057q3dc02.vhd,v 1.6 2007/05/29 09:16:48 jwdonal Exp $ -- -- Description: --- Top level file for the lq057q3dc02 pcore. +-- Top level file for the lq057q3dc02 pcore. The lq057q3dc02 supports QVGA +-- (320x240) mode only! -- -- LCD Handling Cautions: You should make sure that you always power off the -- LCD before turning on the FPGA controller board with the control cable -- connected. -- +-- One useful piece of info for this 320x240x18bpp screen is that the +-- largest amount of image data it can support with all color bits used +-- is 1,382,400 bits = 172,800 bytes. The Virtex-II Pro has enough BRAM +-- space to support 306KB = 313,344 bytes. So you could not possible +-- fill up the BRAM with a single image. +-- +-- NOTE! You can EASILY mistake success for failure when viewing a test +-- image because the resolution of this LCD is soooooo low. Be sure to look +-- VERY carefully at the test image before you assume your algorithms are +-- incorrect! +-- +-- Important Terms: +-- 1 Pixel = 1 [RGB] element on the screen +-- BPP = Bits/Pixel = "Color Depth" = "Bit Depth" +-- BPP/3colors_per_pixel = #BPC = #Bits Per Color +-- 2 color = 1 bpp +-- 16 color = 4 bpp +-- 256 color = 8 bpp +-- 262,144 color = 18 bpp = 6 bpc = this is the same as the lq057q3dc02 +-- 16.7 million color (True Color) = 24 bpp +-- A bitmap file that has anything lower than true color stores it's image +-- data as look-up locations to a color pallete. The color pallete is +-- referenced from the Windows system the bitmap is being viewed on. Remember, +-- "bitmap" is a Microsoft file format! +-- -- Structure: -- - xupv2p.ucf -- - components.vhd @@ -77,56 +103,63 @@ --////////////////////-- ENTITY lq057q3dc02 IS + ----------------------------------------------------------------- + -- Generic Descriptions: + -- + -- C_BIT_DEPTH -- Bit depth of this LCD + -- + -- Video Controller (pass thru) + -- C_RL_STATUS -- Value to use for the RL port + -- C_UD_STATUS -- Value to use for the UD port + -- C_VQ_STATUS -- Value to use for the VQ port + -- + -- VSYNCx Controller (pass thru) + -- C_VSYNC_TV -- VSYNCx cycle time (in lines) + -- C_VSYNC_TVP -- VSYNCx pulse width (in lines) + -- C_VSYNC_TVS -- VSYNCx start position (in lines) - We can't start + -- -- sending data until at least 7 lines have passed + -- -- (i.e. start sending data on the 8th line). + -- + -- HSYNCx Controller (pass thru) + -- C_HSYNC_TH -- HSYNCx cycle time (in clocks) + -- C_HSYNC_THP -- HSYNCx pulse width (in clocks) (maximum pulse width is + -- -- best b/c it will conserver the most power) + -- + -- ENAB Controller (pass thru) + -- C_ENAB_TEP -- ENAB pulse width (in clocks) + -- C_ENAB_THE -- HSYNCx-ENAB phase difference (in clocks) + -- + -- Image Generator (pass thru) + -- Change these when changing the image + -- Also, cleanup all project files, and delete all auto-generated + -- image_gen_bram files. + -- C_BRAM_ADDR_WIDTH -- address width required to access all bytes in + -- -- BRAM image (e.g. a full screen image of 320x240 + -- -- pixels would require an address width of 17) + -- C_IMAGE_WIDTH -- image width (in pixels) + -- C_IMAGE_HEIGHT -- image height (in pixels) + ----------------------------------------------------------------- GENERIC ( - --One useful piece of info for this 320x240x18bpp screen is that the - --largest amount of image data it can support with all color bits used - --is 1,382,400 bits = 172,800 bytes. The Virtex-II Pro has enough BRAM - --space to support 306KB = 313,344 bytes. So you could not possible - --fill up the BRAM with a single image. - - --NOTE! You can EASILY mistake success for failure when viewing a test - --image because the resolution of this LCD is soooooo low. Be sure to look - --VERY carefully at the test image before you assume your algorithms are - --incorrect! + C_BIT_DEPTH : POSITIVE := 18; - --Video Controller (pass thru) C_RL_STATUS : STD_LOGIC := '0'; C_UD_STATUS : STD_LOGIC := '1'; - C_VQ_STATUS : STD_LOGIC := '0'; --This LCD supports QVGA (320x240) mode only! + C_VQ_STATUS : STD_LOGIC := '0'; + + C_VSYNC_TV : POSITIVE := 255; + C_VSYNC_TVP : POSITIVE := 3; + C_VSYNC_TVS : POSITIVE := 7; + + C_HSYNC_TH : POSITIVE := 400; + C_HSYNC_THP : POSITIVE := 10; + + C_ENAB_TEP : POSITIVE := 320; + C_ENAB_THE : POSITIVE := 8; - --Important Terms: - --1 Pixel = 1 [RGB] element on the screen - --BPP = Bits/Pixel = "Color Depth" = "Bit Depth" - --BPP/3colors_per_pixel = #BPC = #Bits Per Color - --2 color = 1 bpp - --16 color = 4 bpp - --256 color = 8 bpp - --262,144 color = 18 bpp = 6 bpc = this is what the lq057q3dc02 is capable of - --16.7 million color (True Color) = 24 bpp - --A bitmap file that has anything lower than true color stores it's image data as look-up locations - --to a color pallete. The color pallete is referenced from the Windows system the bitmap is being viewed on. Remember, Bitmap if a Microsoft file format! - C_BIT_DEPTH : POSITIVE := 18; --2**(18 bits/pixel) = 262,144 possible colors - - --VSYNCx Controller (pass thru) - --MIGHT want to make the TV vector one bit larger in case the ser want to allow for larger time than 255 (the actual time spec can be much larger) - C_VSYNC_TV : POSITIVE := 255; -- VSYNC cycle time (lines) - C_VSYNC_TVP : POSITIVE := 3; -- VSYNCx pulse width (lines) - C_VSYNC_TVS : POSITIVE := 7; -- VSYNCx start position - can NOT start sending data until after 7 lines have passed (i.e. start sending data on the 8th line (i.e exactly THE time the 8th HSYNCx pulse)) - - --HSYNCx Controller (pass thru) - C_HSYNC_TH : POSITIVE := 400; -- HSYNC cycle time (clocks) - C_HSYNC_THP : POSITIVE := 10; -- HSYNCx pulse width (clocks) --would rather have MAX to conserve power (checked as accurate number of cycles in sim, but not on LA) - - --ENAB Controller (pass thru) - C_ENAB_TEP : POSITIVE := 320; -- ENAB Pulse Width (clocks) - C_ENAB_THE : POSITIVE := 8; -- HSYNCx-ENAB Phase Difference (clocks) - - --Change these when changing the image - --Also, cleanup all project files, and delete all auto-generated image_gen_bram files. - C_BRAM_ADDR_WIDTH : POSITIVE := 17; -- required address width for full_screen image of 320x240 pixles - C_IMAGE_WIDTH : POSITIVE := 320; -- in pixels - C_IMAGE_HEIGHT : POSITIVE := 240 -- in pixels + C_BRAM_ADDR_WIDTH : POSITIVE := 17; + C_IMAGE_WIDTH : POSITIVE := 320; + C_IMAGE_HEIGHT : POSITIVE := 240 ); @@ -183,7 +216,7 @@ signal CLK_LCD_wire : std_logic; signal HSYNCx_wire : std_logic; signal VSYNCx_wire : std_logic; - signal LINE_NUM_wire : std_logic_vector(8-1 downto 0); + signal LINE_NUM_wire : std_logic_vector(9-1 downto 0); signal CLK_LCD_CYC_NUM_wire : std_logic_vector(9-1 downto 0); begin @@ -194,7 +227,7 @@ -- LQ057Q3DC02 Datasheet Timing Parameter Checks --TODO: is a check for C_BIT_DEPTH needed? If colors, will just be truncated then that would be kewl. Too high might want to be checked in any case as the colors will not display exactly the same on the LCD. ASSERT C_VQ_STATUS = '0' - REPORT "ERROR - lq057q3dc02: Invalid value for generic C_VQ_STATUS (must be '0', lq057q3dc02 only supports QVGA)" + REPORT "ERROR - lq057q3dc02: Invalid value for generic C_VQ_STATUS (must be '0', lq057q3dc02 only supports QVGA (320x240) mode)" SEVERITY FAILURE; ASSERT C_VSYNC_TV >= 251 and C_VSYNC_TV <= 280 1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/video_controller.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/video_controller.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: video_controller.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/video_controller.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- video_controller.vhd 29 May 2007 08:13:57 -0000 1.2 +++ video_controller.vhd 29 May 2007 09:16:48 -0000 1.3 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: video_controller.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $ +-- $Id: video_controller.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $ -- -- Description: -- This file instantiates the components which control HSYNCx, VSYNCx, ENAB, @@ -82,7 +82,6 @@ C_UD_STATUS, C_VQ_STATUS : STD_LOGIC; - --VSYNC Controller (pass thru) C_VSYNC_TV, C_VSYNC_TVP, @@ -101,9 +100,9 @@ RSTx, CLK_LCD : IN std_logic; - LINE_NUM : OUT std_logic_vector(7 downto 0); + LINE_NUM : OUT std_logic_vector(9-1 downto 0); - CLK_LCD_CYC_NUM : OUT std_logic_vector(8 downto 0); + CLK_LCD_CYC_NUM : OUT std_logic_vector(9-1 downto 0); HSYNCx, VSYNCx, @@ -124,8 +123,8 @@ --Connecting wires between components signal HSYNCx_wire : std_logic; signal VSYNCx_wire : std_logic; - signal LINE_NUM_wire : std_logic_vector(7 downto 0); - signal CLK_LCD_CYC_NUM_wire : std_logic_vector(8 downto 0); + signal LINE_NUM_wire : std_logic_vector(9-1 downto 0); + signal CLK_LCD_CYC_NUM_wire : std_logic_vector(9-1 downto 0); begin 1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/vsyncx_control.vhd http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/vsyncx_control.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: vsyncx_control.vhd =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/vsyncx_control.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- vsyncx_control.vhd 29 May 2007 08:13:57 -0000 1.2 +++ vsyncx_control.vhd 29 May 2007 09:16:48 -0000 1.3 @@ -18,7 +18,7 @@ -- ------------------------------------------------------------------------------ -- --- $Id: vsyncx_control.vhd,v 1.2 2007/05/29 08:13:57 jwdonal Exp $ +-- $Id: vsyncx_control.vhd,v 1.3 2007/05/29 09:16:48 jwdonal Exp $ -- -- Description: -- This file controls VSYNCx. VSYNCx is dependent upon the number of HSYNCx @@ -92,9 +92,19 @@ --////////////////////-- ENTITY vsyncx_control IS + ----------------------------------------------------------------- + -- Generic Descriptions: + -- + -- C_LINE_NUM_WIDTH -- Must be at least 9 bits to hold maximum + -- -- timespec of 280 lines. + ----------------------------------------------------------------- generic ( + C_VSYNC_TV, - C_VSYNC_TVP : POSITIVE + C_VSYNC_TVP : POSITIVE; + + C_LINE_NUM_WIDTH : POSITIVE := 9 + ); port ( @@ -103,7 +113,7 @@ CLK_LCD, HSYNCx : IN STD_LOGIC; - LINE_NUM : OUT STD_LOGIC_VECTOR(7 downto 0); + LINE_NUM : OUT STD_LOGIC_VECTOR(C_LINE_NUM_WIDTH-1 downto 0); VSYNCx : OUT STD_LOGIC @@ -121,7 +131,7 @@ --Stores current line number. --This register is attached to the LINE_NUM output. - signal line_num_reg : std_logic_vector(7 downto 0) := "00000000"; + signal line_num_reg : std_logic_vector(C_LINE_NUM_WIDTH-1 downto 0) := (others => '0'); --------------------------------------------------------------- -- States for VSYNCx_Line_Cntr_*_PROC

     
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