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From: cvs at opencores.org<cvs@o...>
Date: Tue May 29 10:13:58 CEST 2007
Subject: [cvs-checkins] MODIFIED: lq057q3dc02 ...
Date: 00/07/05 29:10:13

Modified: lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye
image_gen_bram_blue.xco image_gen_bram_green.xco
image_gen_bram_red.xco
Log:
Added more file structure notes!


Revision Changes Path
1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_blue.xco

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_blue.xco.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: image_gen_bram_blue.xco
===================================================================
RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_blue.xco,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- image_gen_bram_blue.xco 29 May 2007 07:45:08 -0000 1.2
+++ image_gen_bram_blue.xco 29 May 2007 08:13:58 -0000 1.3
@@ -1,8 +1,51 @@
+##############################################################################
+# Copyright (C) 2007 Jonathon W. Donaldson
+# jwdonal a t opencores DOT org
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+##############################################################################
+#
+# $Id: image_gen_bram_blue.xco,v 1.3 2007/05/29 08:13:58 jwdonal Exp $
+#
+# Description:
+# XCO file automatically generated by the Xilinx CoreGen tool.
+#
+# Structure:
+# - xupv2p.ucf
+# - components.vhd
+# - lq057q3dc02_tb.vhd
+# - lq057q3dc02.vhd
+# - dcm_sys_to_lcd.xaw
+# - video_controller.vhd
+# - enab_control.vhd
+# - hsyncx_control.vhd
+# - vsyncx_control.vhd
+# - clk_lcd_cyc_cntr.vhd
+# - image_gen_bram.vhd
+# - image_gen_bram_red.xco
+# - image_gen_bram_green.xco
+# - image_gen_bram_blue.xco
+#
+##############################################################################
+
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
-SET workingdirectory = ..\ise_files
+SET workingdirectory =..\ise_files
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = True
@@ -34,8 +77,8 @@
CSET enable_pin_polarity=Active_High
CSET component_name=image_gen_bram_blue
CSET active_clock_edge=Rising_Edge_Triggered
-CSET disable_warning_messages=true
CSET additional_output_pipe_stages=0
+CSET disable_warning_messages=true
CSET limit_data_pitch=18
CSET primitive_selection=Optimize_For_Area
CSET enable_pin=false
@@ -47,3 +90,4 @@
CSET register_inputs=false
# END Parameters
GENERATE
+



1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_green.xco

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_green.xco.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: image_gen_bram_green.xco
=================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_green.xco,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- image_gen_bram_green.xco 29 May 2007 07:45:08 -0000 1.2 +++ image_gen_bram_green.xco 29 May 2007 08:13:58 -0000 1.3 @@ -1,3 +1,46 @@ +############################################################################## +# Copyright (C) 2007 Jonathon W. Donaldson +# jwdonal a t opencores DOT org +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +############################################################################## +# +# $Id: image_gen_bram_green.xco,v 1.3 2007/05/29 08:13:58 jwdonal Exp $ +# +# Description: +# XCO file automatically generated by the Xilinx CoreGen tool. +# +# Structure: +# - xupv2p.ucf +# - components.vhd +# - lq057q3dc02_tb.vhd +# - lq057q3dc02.vhd +# - dcm_sys_to_lcd.xaw +# - video_controller.vhd +# - enab_control.vhd +# - hsyncx_control.vhd +# - vsyncx_control.vhd +# - clk_lcd_cyc_cntr.vhd +# - image_gen_bram.vhd +# - image_gen_bram_red.xco +# - image_gen_bram_green.xco +# - image_gen_bram_blue.xco +# +############################################################################## + # BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True @@ -24,7 +67,7 @@ # BEGIN Parameters CSET handshaking_pins=false CSET init_value=0 -CSET coefficient_file=..\src\full_screen_G.coe +CSET coefficient_file = ..\src\full_screen_G.coe CSET select_primitive=16kx1 CSET initialization_pin_polarity=Active_Low CSET global_init_value=0 @@ -34,8 +77,8 @@ CSET enable_pin_polarity=Active_High CSET component_name=image_gen_bram_green CSET active_clock_edge=Rising_Edge_Triggered -CSET disable_warning_messages=true CSET additional_output_pipe_stages=0 +CSET disable_warning_messages=true CSET limit_data_pitch=18 CSET primitive_selection=Optimize_For_Area CSET enable_pin=false 1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_red.xco http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_red.xco.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: image_gen_bram_red.xco =================================================================== RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/image_gen_bram_files/tie_dye/image_gen_bram_red.xco,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- image_gen_bram_red.xco 29 May 2007 07:45:08 -0000 1.2 +++ image_gen_bram_red.xco 29 May 2007 08:13:58 -0000 1.3 @@ -1,3 +1,46 @@ +############################################################################## +# Copyright (C) 2007 Jonathon W. Donaldson +# jwdonal a t opencores DOT org +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +# +############################################################################## +# +# $Id: image_gen_bram_red.xco,v 1.3 2007/05/29 08:13:58 jwdonal Exp $ +# +# Description: +# XCO file automatically generated by the Xilinx CoreGen tool. +# +# Structure: +# - xupv2p.ucf +# - components.vhd +# - lq057q3dc02_tb.vhd +# - lq057q3dc02.vhd +# - dcm_sys_to_lcd.xaw +# - video_controller.vhd +# - enab_control.vhd +# - hsyncx_control.vhd +# - vsyncx_control.vhd +# - clk_lcd_cyc_cntr.vhd +# - image_gen_bram.vhd +# - image_gen_bram_red.xco +# - image_gen_bram_green.xco +# - image_gen_bram_blue.xco +# +############################################################################## + # BEGIN Project Options SET flowvendor = Foundation_iSE SET vhdlsim = True @@ -24,7 +67,7 @@ # BEGIN Parameters CSET handshaking_pins=false CSET init_value=0 -CSET coefficient_file=..\src\full_screen_R.coe +CSET coefficient_file = ..\src\full_screen_R.coe CSET select_primitive=16kx1 CSET initialization_pin_polarity=Active_Low CSET global_init_value=0 @@ -34,8 +77,8 @@ CSET enable_pin_polarity=Active_High CSET component_name=image_gen_bram_red CSET active_clock_edge=Rising_Edge_Triggered -CSET disable_warning_messages=true CSET additional_output_pipe_stages=0 +CSET disable_warning_messages=true CSET limit_data_pitch=18 CSET primitive_selection=Optimize_For_Area CSET enable_pin=false