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From: cvs at opencores.org<cvs@o...>
Date: Tue May 29 09:57:57 CEST 2007
Subject: [cvs-checkins] MODIFIED: lq057q3dc02 ...
Date: 00/07/05 29:09:57

Modified: lq057q3dc02/hdl/vhsic/coe_image_gen lq057q3dc02.vhd
Log:
Comments


Revision Changes Path
1.4 lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: lq057q3dc02.vhd
===================================================================
RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- lq057q3dc02.vhd 29 May 2007 07:29:41 -0000 1.3
+++ lq057q3dc02.vhd 29 May 2007 07:57:57 -0000 1.4
@@ -18,7 +18,7 @@
--
------------------------------------------------------------------------------
--
--- $Id: lq057q3dc02.vhd,v 1.3 2007/05/29 07:29:41 jwdonal Exp $
+-- $Id: lq057q3dc02.vhd,v 1.4 2007/05/29 07:57:57 jwdonal Exp $
--
-- Description:
-- Top level file for the lq057q3dc02 pcore.
@@ -246,7 +246,7 @@
CLKIN_IN => CLK_100M_PAD,
CLKIN_IBUFG_OUT => OPEN, -- 100MHz clock if you need it (attach to BUFG)
CLK0_OUT => OPEN, -- 50MHz clock
- CLKDV_OUT => CLK_LCD_wire,
+ CLKDV_OUT => CLK_LCD_wire, -- 6.25MHz LCD Clock
CLKFX_OUT => OPEN -- Attach this 25MHz clock to an output port for a logic analyzer
);