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From: cvs at opencores.org<cvs@o...>
Date: Tue May 29 09:29:42 CEST 2007
Subject: [cvs-checkins] MODIFIED: lq057q3dc02 ...
Date: 00/07/05 29:09:29

Modified: lq057q3dc02/hdl/vhsic/coe_image_gen lq057q3dc02.vhd
Log:
Added port descriptions.


Revision Changes Path
1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: lq057q3dc02.vhd
===================================================================
RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- lq057q3dc02.vhd 25 May 2007 11:27:37 -0000 1.2
+++ lq057q3dc02.vhd 29 May 2007 07:29:41 -0000 1.3
@@ -18,7 +18,7 @@
--
------------------------------------------------------------------------------
--
--- $Id: lq057q3dc02.vhd,v 1.2 2007/05/25 11:27:37 jwdonal Exp $
+-- $Id: lq057q3dc02.vhd,v 1.3 2007/05/29 07:29:41 jwdonal Exp $
--
-- Description:
-- Top level file for the lq057q3dc02 pcore.
@@ -129,6 +129,26 @@

);

+ -----------------------------------------------------------------
+ -- Port Descriptions:
+ -- INPUTS
+ -- --Clocks/Resets--
+ -- RSTx -- System Reset
+ -- CLK100_PAD -- 100MHz Input Clock from On-board XTAL
+ --
+ -- OUTPUTS
+ -- --LCD Control Signals--
+ -- CLK_LCD -- 6.25MHz LCD Clock
+ -- HSYNCx -- Horizontal Sync Strobe
+ -- VSYNCx -- Vertical Sync Strobe
+ -- ENAB -- Enable Signal for LCD's shift registers
+ -- RL -- LCD Image Right/Left Orientation
+ -- UD -- LCD Image Up/Down Orientation
+ -- VQ -- VGA (640x480) or QVGA (320x240) mode
+ --
+ -- --LCD Data Signals--
+ -- R,G,B -- Red/Green/Blue Color Data
+ -----------------------------------------------------------------
PORT (

-- <PORT_NAME> : <MODE> <DATA_TYPE>;