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From: cvs at opencores.org<cvs@o...>
Date: Sat May 26 21:41:56 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/07/05 26:21:41

Modified: jop/doc/book/intro directory.tex
Log:
no message


Revision Changes Path
1.2 jop/doc/book/intro/directory.tex

http://www.opencores.org/cvsweb.shtml/jop/doc/book/intro/directory.tex.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: directory.tex
===================================================================
RCS file: /cvsroot/martin/jop/doc/book/intro/directory.tex,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- directory.tex 26 May 2007 19:05:28 -0000 1.1
+++ directory.tex 26 May 2007 19:41:55 -0000 1.2
@@ -8,7 +8,7 @@
\item[bat] Old batch files - \emph{not used}
\item[boards] Pictures and text for the Eclipse plugin
\item[c\_src] Some utilities in C (e.g.\ \cmd{down.exe} and
- \cmd{e.exe}.
+ \cmd{e.exe}).
\item[doc] \LaTeX sources for this handbook and short notes.
\item[eclipse] Eclipse project files
\item[ext] External VHDL and Verilog sources
@@ -17,19 +17,53 @@
\item[lib] External .jar files
\item[pc] Tools on the PC
\item[pcsim] High-level simulation on the PC
- \item[target] THE Java sources for JOP
+ \item[target] \emph{The} Java sources for JOP
\item[tools] All Java tools
\end{description}
- \item[jbc] (generated)
- \item[jopc]
- \item[linux]
- \item[modelsim]
- \item[pins]
- \item[quartus]
- \item[rbf]
- \item[sopc]
- \item[support]
- \item[ttf] (generated)
- \item[vhdl]
- \item[xilinx]
+ \item[jbc] FPGA configuration files for \cmd{jbi32.exe} (generated)
+ \item[jopc] A C version of a JOP JVM simulation -- \emph{very} outdated
+ \item[linux] Scripts to start a network and SLIP
+ \item[modelsim] ModelSim simulation
+ \item[pins] Pin definitions for FPGA boards
+ \item[quartus] Quartus project files
+ \item[rbf] FPGA configuration files for USBRunner (generated)
+ \item[sopc] JOP as SoPC component and SRAM components
+ \item[support] Stand-alone Flash programming for the Cycore board
+ \item[ttf] FPGA configuration files for Flash programming (generated)
+ \item[vhdl] The processor sources
+ \begin{description}
+ \item[altera] Altera specific components (PLL, RAM)
+ \item[config] Cycore PLD sources
+ \item[core] The processor core
+ \item[fpu] The floating-point unit -- \emph{not used}
+ \item[memory] Main memory connections vi SimpCon
+ \item[scio] IO components and configurations with SimpCon
+ \item[simpcon] SimpCon bridges and arbiter
+ \item[simulation] Memory and UART for ModelSim simulation
+ \item[start] The VHDL version of \emph{hello world} -- a blinking
+ LED
+ \item[testbenches] no real content
+ \item[top] Top-level and configuration (e.g.\ PLL setting) components
+ \item[vga] A SimpCon VGA controller
+ \item[wishbone] WISHBONE files -- \emph{not used?}
+ \item[xilinx] Xilinx specific components (RAM)
+ \end{description}
+ \item[xilinx] Xilins project files
+\end{description}
+
+\subsection{The Java Sources for JOP}
+
+The most important directory for all Java sources that run on JOP is
+in \dirent{java/target}.
+
+\begin{description}
+ \item[dist] Generated files
+ \begin{description}
+ \item[bin] The linked application (\code{.jop})
+ \item[classes] The class files
+ \item[lib] The application class files in \code{classes.zip}
+ -- input for \cmd{JOPizer}
+ \end{description}
+ \item[src] The source
+ \item[wcet] Output from the WCET analyzer (generated)
\end{description}