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From: cvs at opencores.org<cvs@o...>
Date: Fri May 25 20:43:36 CEST 2007
Subject: [cvs-checkins] MODIFIED: lq057q3dc02 ...
Date: 00/07/05 25:20:43

Modified: lq057q3dc02/hdl/vhsic/coe_image_gen lq057q3dc02.tcl
Log:
Added missing project options


Revision Changes Path
1.3 lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.tcl

http://www.opencores.org/cvsweb.shtml/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.tcl.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: lq057q3dc02.tcl
===================================================================
RCS file: /cvsroot/jwdonal/lq057q3dc02/hdl/vhsic/coe_image_gen/lq057q3dc02.tcl,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- lq057q3dc02.tcl 25 May 2007 11:31:36 -0000 1.2
+++ lq057q3dc02.tcl 25 May 2007 18:43:36 -0000 1.3
@@ -15,6 +15,15 @@
project set synthesis_tool "XST (VHDL/Verilog)"
project set generated_simulation_language "ModelSim-SE Mixed"

+# Set Generate Programming File properties
+project set "Unused IOB Pins" "Pull Up"
+project set "FPGA Start-Up Clock" "JTAG Clock"
+project set "Done (Output Events)" 6
+project set "Enable Outputs (Output Events)" 3
+project set "Release Write Enable (Output Events)" 5
+project set "Release DLL (Output Events)" 4
+
+
# Go back to user source directory
cd ../coe_image_gen