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From: cvs at opencores.org<cvs@o...>
Date: Mon Apr 30 17:58:31 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 30:17:58

Modified: aemb/rtl/verilog aeMB_decode.v
Log:
Fixed minor data hazard bug spotted by Matt Ettus.


Revision Changes Path
1.8 aemb/rtl/verilog/aeMB_decode.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_decode.v.diff?r1=1.7&r2=1.8

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_decode.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_decode.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- aeMB_decode.v 27 Apr 2007 04:23:17 -0000 1.7
+++ aeMB_decode.v 30 Apr 2007 15:58:31 -0000 1.8
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_decode.v,v 1.7 2007/04/27 04:23:17 sybreon Exp $
+ * $Id: aeMB_decode.v,v 1.8 2007/04/30 15:58:31 sybreon Exp $
*
* AEMB Instruction Decoder
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: aeMB_decode.v,v $
+ * Revision 1.8 2007/04/30 15:58:31 sybreon
+ * Fixed minor data hazard bug spotted by Matt Ettus.
+ *
* Revision 1.7 2007/04/27 04:23:17 sybreon
* Removed some unnecessary bubble control.
*
@@ -89,7 +92,7 @@
TODO: Modify this for block RAM based instruction cache.
*/
wire [31:0] wIREG;
- assign wIREG = {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]};
+ assign wIREG = iwb_dat_i;

wire [5:0] wOPC = wIREG[31:26];
wire [4:0] wRD = wIREG[25:21];
@@ -248,7 +251,7 @@
*/

reg [1:0] rMXSRC, rMXTGT, rMXALT, xMXSRC,xMXTGT,xMXALT;
- wire fRWE = (|rRD) & !(&rMXBRA);
+ wire fRWE = (|rRD) & !(&rMXBRA) & !(|rMXLDST);

always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or rMXLDST or rRD
or wOPC or wRA or wRB) begin // frun