Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: cvs at opencores.org<cvs@o...>
Date: Mon Apr 30 17:56:50 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 30:17:56

Modified: aemb/rtl/verilog aeMB_aslu.v aeMB_regfile.v
Log:
Removed byte acrobatics.


Revision Changes Path
1.8 aemb/rtl/verilog/aeMB_aslu.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_aslu.v.diff?r1=1.7&r2=1.8

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_aslu.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_aslu.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- aeMB_aslu.v 27 Apr 2007 00:23:55 -0000 1.7
+++ aeMB_aslu.v 30 Apr 2007 15:56:50 -0000 1.8
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_aslu.v,v 1.7 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_aslu.v,v 1.8 2007/04/30 15:56:50 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_aslu.v,v $
+ * Revision 1.8 2007/04/30 15:56:50 sybreon
+ * Removed byte acrobatics.
+ *
* Revision 1.7 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -61,7 +64,6 @@

output [DSIZ-1:0] dwb_adr_o;
output [3:0] dwb_sel_o;
- //input [31:0] dwb_dat_i;

output [31:0] rRESULT;
output [3:0] rDWBSEL;
@@ -213,7 +215,7 @@

reg [3:0] rDWBSEL, xDWBSEL;
assign dwb_adr_o = {rRESULT[DSIZ-1:2],2'b00};
- assign dwb_sel_o = {rDWBSEL[0],rDWBSEL[1],rDWBSEL[2],rDWBSEL[3]};
+ assign dwb_sel_o = rDWBSEL;

always @(/*AUTOSENSE*/rOPC or wADD)
case (wADD[1:0])



1.15 aemb/rtl/verilog/aeMB_regfile.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.14&r2=1.15

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -b -r1.14 -r1.15
--- aeMB_regfile.v 27 Apr 2007 15:15:49 -0000 1.14
+++ aeMB_regfile.v 30 Apr 2007 15:56:50 -0000 1.15
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.14 2007/04/27 15:15:49 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.15 2007/04/30 15:56:50 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -27,6 +27,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.15 2007/04/30 15:56:50 sybreon
+ * Removed byte acrobatics.
+ *
* Revision 1.14 2007/04/27 15:15:49 sybreon
* Fixed simulation bug.
*
@@ -143,8 +146,8 @@
wire [31:0] wDWBDAT;
reg [31:0] sDWBDAT;
reg [31:0] rDWBDAT;
- assign dwb_dat_o = {rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
- assign wDWBDAT = {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+ assign dwb_dat_o = rDWBDAT;
+ assign wDWBDAT = dwb_dat_i;

/**
RAM Based Register File