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From: cvs at opencores.org<cvs@o...>
Date: Mon Apr 30 17:56:50 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 30:17:56

Modified: aemb/sim/verilog testbench.v
Log:
Removed byte acrobatics.


Revision Changes Path
1.4 aemb/sim/verilog/testbench.v

http://www.opencores.org/cvsweb.shtml/aemb/sim/verilog/testbench.v.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: testbench.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/sim/verilog/testbench.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- testbench.v 27 Apr 2007 15:18:43 -0000 1.3
+++ testbench.v 30 Apr 2007 15:56:50 -0000 1.4
@@ -1,5 +1,5 @@
/*
- * $Id: testbench.v,v 1.3 2007/04/27 15:18:43 sybreon Exp $
+ * $Id: testbench.v,v 1.4 2007/04/30 15:56:50 sybreon Exp $
*
* AEMB Generic Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: testbench.v,v $
+ * Revision 1.4 2007/04/30 15:56:50 sybreon
+ * Removed byte acrobatics.
+ *
* Revision 1.3 2007/04/27 15:18:43 sybreon
* Minor updates as sw/c/aeMB_testbench.c got updated.
*
@@ -47,8 +50,8 @@
always #5 sys_clk_i = ~sys_clk_i;

initial begin
- $dumpfile("dump.vcd");
- $dumpvars(1,dut);
+ //$dumpfile("dump.vcd");
+ //$dumpvars(1,dut);
end

initial begin
@@ -85,9 +88,9 @@
wire [DSIZ-1:0] dwb_adr_o;
wire [31:0] dwb_dat_t;

- assign dwb_dat_i = ram[dadr];
- assign iwb_dat_i = ram[iadr];
- assign dwb_dat_t = ram[dwb_adr_o[DSIZ-1:2]];
+ assign {dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
+ assign {iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
+ assign {dwb_dat_t} = ram[dwb_adr_o[DSIZ-1:2]];

always @(posedge sys_clk_i) begin
iwb_ack_i <= #1 iwb_stb_o;
@@ -97,13 +100,13 @@

if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
- 4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:8],dwb_dat_o[7:0]};
- 4'h2: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[15:8],dwb_dat_t[7:0]};
- 4'h4: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:24],dwb_dat_o[23:16],dwb_dat_t[15:0]};
- 4'h8: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:24],dwb_dat_t[23:0]};
- 4'h3: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[15:0]};
- 4'hC: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:16],dwb_dat_t[15:0]};
- 4'hF: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:0]};
+ 4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
+ 4'h2: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
+ 4'h4: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]};
+ 4'h8: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:8],dwb_dat_o[31:24]};
+ 4'h3: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]};
+ 4'hC: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]};
+ 4'hF: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
endcase // case (dwb_sel_o)
end
end
@@ -111,7 +114,7 @@
integer i;
initial begin
for (i=0;i<65535;i=i+1) begin
- ram[i] <= 32'h0;
+ ram[i] <= $random;
end
#1 $readmemh("aeMB.rom",ram);
end
@@ -142,7 +145,7 @@
if (dwb_we_o & (dwb_dat_o == "PASS")) begin
$display("\tPASS");
end
- if (iwb_dat_i == 32'h000000b8) begin
+ if (iwb_dat_i == 32'hb8000000) begin
$display("\n\t*** PASSED ALL TESTS ***");
$finish;
end