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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Fri Apr 27 06:23:18 CEST 2007
    Subject: [cvs-checkins] MODIFIED: aemb ...
    Top
    Date: 00/07/04 27:06:23

    Modified: aemb/rtl/verilog aeMB_decode.v
    Log:
    Removed some unnecessary bubble control.


    Revision Changes Path
    1.7 aemb/rtl/verilog/aeMB_decode.v

    http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_decode.v.diff?r1=1.6&r2=1.7

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: aeMB_decode.v
    ===================================================================
    RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_decode.v,v
    retrieving revision 1.6
    retrieving revision 1.7
    diff -u -b -r1.6 -r1.7
    --- aeMB_decode.v 27 Apr 2007 00:23:55 -0000 1.6
    +++ aeMB_decode.v 27 Apr 2007 04:23:17 -0000 1.7
    @@ -1,5 +1,5 @@
    /*
    - * $Id: aeMB_decode.v,v 1.6 2007/04/27 00:23:55 sybreon Exp $
    + * $Id: aeMB_decode.v,v 1.7 2007/04/27 04:23:17 sybreon Exp $
    *
    * AEMB Instruction Decoder
    * Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
    @@ -24,6 +24,9 @@
    *
    * HISTORY
    * $Log: aeMB_decode.v,v $
    + * Revision 1.7 2007/04/27 04:23:17 sybreon
    + * Removed some unnecessary bubble control.
    + *
    * Revision 1.6 2007/04/27 00:23:55 sybreon
    * Added code documentation.
    * Improved size & speed of rtl/verilog/aeMB_aslu.v
    @@ -174,19 +177,13 @@
    */

    reg [1:0] rMXALU, xMXALU;
    - always @(/*AUTOSENSE*/fBRA or fLOGIC or fSHIFT or frun)
    - if (frun) begin
    + always @(/*AUTOSENSE*/fBRA or fLOGIC or fSHIFT) begin // frun
    xMXALU <= //(!fNBR) ? 2'o0 :
    (fSHIFT) ? 2'o2 :
    (fLOGIC) ? 2'o1 :
    (fBRA) ? 2'o3 :
    2'o0;
    - end else begin
    - /*AUTORESET*/
    - // Beginning of autoreset for uninitialized flops
    - xMXALU <= 2'h0;
    - // End of automatics
    - end // else: !if(frun)
    + end

    /**
    BCC/BRA/RET
    @@ -209,17 +206,19 @@
    (fRET) ? 1'b1 :
    (fBRU) ? wRA[4] :
    1'b0;
    - xMXLNK <= //(!fNBR) ? 1'b0 :
    - (fBRU) ? wRA[2] : 1'b0;
    end else begin // if (frun)
    /*AUTORESET*/
    // Beginning of autoreset for uninitialized flops
    xMXBRA <= 2'h0;
    xMXDLY <= 1'h0;
    - xMXLNK <= 1'h0;
    // End of automatics
    end // else: !if(frun)

    + always @(/*AUTOSENSE*/fBRU or wRA) begin
    + xMXLNK <= //(!fNBR) ? 1'b0 :
    + (fBRU) ? wRA[2] : 1'b0;
    + end
    +
    /**
    LD/ST
    -----
    @@ -235,7 +234,7 @@
    (fST) ? 2'o3 :
    2'o0;
    end else begin
    - /*AUTORESET*/
    + /*UTORESET*/
    // Beginning of autoreset for uninitialized flops
    xMXLDST <= 2'h0;
    // End of automatics
    @@ -249,11 +248,10 @@
    */

    reg [1:0] rMXSRC, rMXTGT, rMXALT, xMXSRC,xMXTGT,xMXALT;
    - wire fRWE = (rRD != 5'd0) & (rMXBRA != 2'o3);
    + wire fRWE = (|rRD) & !(&rMXBRA);

    - always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or frun or rMXLDST
    - or rRD or wOPC or wRA or wRB)
    - if (frun) begin + always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or rMXLDST or rRD + or wOPC or wRA or wRB) begin // frun xMXSRC <= //(!fNBR) ? 2'o0 : (fBRU|fBCC) ? 2'o1 : // PC ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB @@ -269,14 +267,7 @@ ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB ((rRD == wRA) & fRWE) ? 2'o2 : // FWD 2'o0; // RA - end else begin // if (frun) - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xMXALT <= 2'h0; - xMXSRC <= 2'h0; - xMXTGT <= 2'h0; - // End of automatics - end // else: !if(frun) + end // always @ (... /** IMM Latching @@ -289,19 +280,11 @@ reg [15:0] rIMMHI, xIMMHI; reg rFIMM, xFIMM; - always @(/*AUTOSENSE*/fIMM or frun or rFIMM or rIMMHI or wIMM) - if (frun) begin + always @(/*AUTOSENSE*/fIMM or rFIMM or rIMMHI or wIMM) begin // frun xSIMM <= (rFIMM) ? {rIMMHI,wIMM} : {{(16){wIMM[15]}},wIMM}; xFIMM <= fIMM; xIMMHI <= (fIMM) ? wIMM : rIMMHI; - end else begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - xFIMM <= 1'h0; - xIMMHI <= 16'h0; - xSIMM <= 32'h0; - // End of automatics - end // else: !if(frun) + end /** COMPARATOR @@ -377,6 +360,7 @@ This signal controls the flag that determines whether a D register is open for writing. */ + reg rRWE, xRWE; wire wRWE = |rRD; always @(/*AUTOSENSE*/drun or rMXBRA or rMXLDST or wRWE) @@ -420,7 +404,7 @@ always @(negedge nclk or negedge nrst) if (!nrst) begin - rOPC <= 6'o40; + //rOPC <= 6'o40; /*AUTORESET*/ // Beginning of autoreset for uninitialized flops rBRA <= 1'h0; @@ -439,6 +423,7 @@ rMXLNK <= 1'h0; rMXSRC <= 2'h0; rMXTGT <= 2'h0; + rOPC <= 6'h0; rRA <= 5'h0; rRB <= 5'h0; rRD <= 5'h0;

     
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