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From: cvs at opencores.org<cvs@o...>
Date: Fri Apr 27 06:22:40 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 27:06:22

Modified: aemb/rtl/verilog aeMB_regfile.v
Log:
Fixed minor synthesis bug.


Revision Changes Path
1.13 aemb/rtl/verilog/aeMB_regfile.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.12&r2=1.13

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -b -r1.12 -r1.13
--- aeMB_regfile.v 27 Apr 2007 00:23:55 -0000 1.12
+++ aeMB_regfile.v 27 Apr 2007 04:22:40 -0000 1.13
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.12 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.13 2007/04/27 04:22:40 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -27,6 +27,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.13 2007/04/27 04:22:40 sybreon
+ * Fixed minor synthesis bug.
+ *
* Revision 1.12 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -75,7 +78,7 @@
dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRESULT, rFSM, rPC,
rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
);
- // Data WB address bus width
+ // FIXME: This parameter is not used here.
parameter DSIZ = 32;

// Data WB Signals
@@ -95,15 +98,6 @@
input rLNK, rRWE;
input nclk, nrst, drun, nrun;

- // ASYNCHRONOUS ////////////////////////////////////////////////////////////////////
-
- wire [31:0] wRESULT;
- wire fWE = rRWE & !rDWBWE;
- wire fLNK = rLNK;
- wire fLD = rDWBSTB ^ rDWBWE;
- wire fDFWD = !(rRD ^ rRD_) & fWE;
- wire fMFWD = rDWBSTB & !rDWBWE;
-
/**
Delay Latches
----------
@@ -122,6 +116,19 @@
end

/**
+ Control Flags
+ -------------
+ Various internal flags.
+ */
+
+ wire [31:0] wRESULT;
+ wire fWE = rRWE & !rDWBWE;
+ wire fLNK = rLNK;
+ wire fLD = rDWBSTB ^ rDWBWE;
+ wire fDFWD = !(rRD ^ rRD_) & fWE;
+ wire fMFWD = rDWBSTB & !rDWBWE;
+
+ /**
Data WISHBONE Bus
-----------------
The data word that is read or written between the core and the
@@ -220,6 +227,7 @@
The register file is initialised with random values to reflect a
realistic situation where the values are undefined at power-up.
*/
+ // synopsys translate_off
integer i;
initial begin
for (i=0;i<31;i=i+1) begin
@@ -228,6 +236,7 @@
rMEMD[i] <= $random;
end
end
+ // synopsys translate_on

endmodule // aeMB_regfile