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Message
From: cvs at opencores.org<cvs@o...>
Date: Thu Apr 26 00:52:53 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 26:00:52 Modified: aemb/rtl/verilog aeMB_regfile.v
Log:
Fixed minor simulation bug.
Revision Changes Path
1.10 aemb/rtl/verilog/aeMB_regfile.v
http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- aeMB_regfile.v 25 Apr 2007 22:15:04 -0000 1.9
+++ aeMB_regfile.v 25 Apr 2007 22:52:53 -0000 1.10
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.9 2007/04/25 22:15:04 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.10 2007/04/25 22:52:53 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.10 2007/04/25 22:52:53 sybreon
+ * Fixed minor simulation bug.
+ *
* Revision 1.9 2007/04/25 22:15:04 sybreon
* Added support for 8-bit and 16-bit data types.
*
@@ -120,12 +123,12 @@
always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
case (rDWBSEL)
4'hF: sDWBDAT <= wDWBDAT;
- 4'hC: sDWBDAT <= {(16){1'b0},wDWBDAT[31:16]};
- 4'h3: sDWBDAT <= {(16){1'b0},wDWBDAT[15:0]};
- 4'h8: sDWBDAT <= {(24){1'b0},wDWBDAT[31:24]};
- 4'h4: sDWBDAT <= {(24){1'b0},wDWBDAT[23:16]};
- 4'h2: sDWBDAT <= {(24){1'b0},wDWBDAT[15:8]};
- 4'h1: sDWBDAT <= {(24){1'b0},wDWBDAT[7:0]};
+ 4'hC: sDWBDAT <= {16'd0,wDWBDAT[31:16]};
+ 4'h3: sDWBDAT <= {16'd0,wDWBDAT[15:0]};
+ 4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
+ 4'h4: sDWBDAT <= {24'd0,wDWBDAT[23:16]};
+ 4'h2: sDWBDAT <= {24'd0,wDWBDAT[15:8]};
+ 4'h1: sDWBDAT <= {24'd0,wDWBDAT[7:0]};
default: sDWBDAT <= 32'h0;
endcase // case (rDWBSEL)
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