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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Apr 21 20:57:15 CEST 2007
Subject: [cvs-checkins] MODIFIED: mlite ...
Date: 00/07/04 21:20:57 Modified: mlite/vhdl pipeline.vhd
Log:
Added comment about delaying reg_dest
Revision Changes Path
1.9 mlite/vhdl/pipeline.vhd
http://www.opencores.org/cvsweb.shtml/mlite/vhdl/pipeline.vhd.diff?r1=1.8&r2=1.9
(In the diff below, changes in quantity of whitespace are not shown.)
Index: pipeline.vhd
===================================================================
RCS file: /cvsroot/rhoads/mlite/vhdl/pipeline.vhd,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- pipeline.vhd 6 Mar 2006 02:07:03 -0000 1.8
+++ pipeline.vhd 21 Apr 2007 18:57:15 -0000 1.9
@@ -76,6 +76,16 @@
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
+ -- The value written back into the register bank, signal reg_dest is tricky.
+ -- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
+ -- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
+ -- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
+ -- stage #3.
+ -- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
+ -- are multiplexed into reg_dest which is then delayed. The decision to use
+ -- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
+ -- based on a delayed value of c_source (c_source_reg).
+
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
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