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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Mon Apr 16 22:00:19 CEST 2007
    Subject: [cvs-checkins] MODIFIED: djpeg ...
    Top
    Date: 00/07/04 16:22:00

    Modified: djpeg/src jpeg_decode.v jpeg_decode_fsm.v jpeg_dht.v
    jpeg_hm_decode.v jpeg_idctx.v jpeg_idcty.v
    jpeg_regdata.v jpeg_ycbcr_mem.v jpeg_ziguzagu_reg.v
    Log:
    update




    Revision Changes Path
    1.2 djpeg/src/jpeg_decode.v

    http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_decode.v.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: jpeg_decode.v
    ===================================================================
    RCS file: /cvsroot/hidemi/djpeg/src/jpeg_decode.v,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- jpeg_decode.v 5 Oct 2006 04:45:15 -0000 1.1
    +++ jpeg_decode.v 16 Apr 2007 20:00:18 -0000 1.2
    @@ -7,15 +7,14 @@
    // Author : H.Ishihara
    // E-Mail : hidemi@s...
    // HomePage : http://www.sweetcafe.jp/
    -// Date : 2006/10/01
    -// Rev. : 1.1
    +// Date : 2007/04/11
    +// Rev. : 2.0
    //---------------------------------------------------------------------------
    // Rev. Date Description
    //---------------------------------------------------------------------------
    // 1.01 2006/10/01 1st Release
    // 1.02 2006/10/04 add ProcessIdle register
    -//---------------------------------------------------------------------------
    -// $Id:
    +// 2.00 2007/04/11
    //---------------------------------------------------------------------------
    `timescale 1ps / 1ps

    @@ -29,7 +28,6 @@
    DataInEnable,
    DataInRead,

    - JpegDecodeStart, //
    JpegDecodeIdle, // Deocdeer Process Idle(1:Idle, 0:Run)

    OutEnable,
    @@ -50,7 +48,6 @@
    input DataInEnable;
    output DataInRead;

    - input JpegDecodeStart;
    output JpegDecodeIdle;

    output OutEnable;
    @@ -64,7 +61,7 @@

    wire [31:0] JpegData;
    wire JpegDataEnable;
    - wire JpegDataEnd;
    + wire JpegDecodeIdle;

    wire UseBit;
    wire [6:0] UseWidth;
    @@ -73,6 +70,9 @@

    wire ImageEnable;
    wire EnableFF00;
    + wire DecodeFinish;
    +
    +// reg ProcessIdle;

    //--------------------------------------------------------------------------
    // Read JPEG Data from FIFO
    @@ -82,7 +82,6 @@
    .clk(clk),

    // Read Data
    - .DataInStart ( JpegDecodeStart ),
    .DataIn ( DataIn ),
    .DataInEnable ( DataInEnable ),
    .DataInRead ( DataInRead ),
    @@ -90,10 +89,10 @@
    // DataOut
    .DataOut ( JpegData ),
    .DataOutEnable ( JpegDataEnable ),
    - .DataOutEnd ( JpegDataEnd ),

    //
    .ImageEnable ( EnableFF00 ),
    + .ProcessIdle ( JpegDecodeIdle ),

    // UseData
    .UseBit ( UseBit ),
    @@ -132,12 +131,14 @@
    .DataInEnable ( JpegDataEnable ),
    .DataIn ( JpegData ), - .JpegDecodeStart ( JpegDecodeStart ), - .JpegDecodeIdle ( ), + .JpegDecodeIdle ( JpegDecodeIdle ), .OutWidth ( OutWidth ), .OutHeight ( OutHeight ), .OutBlockWidth ( JpegBlockWidth ), + .OutEnable ( OutEnable ), + .OutPixelX ( OutPixelX ), + .OutPixelY ( OutPixelY ), // .DqtEnable ( DqtEnable ), @@ -160,7 +161,7 @@ // .ImageEnable ( ImageEnable ), - .ImageEnd ( JpegDataEnd ), + .ImageEnd ( DecodeFinish ), .EnableFF00 ( EnableFF00 ), // @@ -440,6 +441,9 @@ .Data1Out ( Dct1Data ) ); + wire ColorEnable; + wire [15:0] ColorPixelX, ColorPixelY; + wire [7:0] ColorR, ColorG, ColorB; jpeg_ycbcr u_jpeg_ycbcr( .rst(rst), .clk(clk), @@ -452,27 +456,19 @@ .Data1In ( Dct1Data ), .DataInBlockWidth ( JpegBlockWidth ), - .OutEnable ( OutEnable ), - .OutPixelX ( OutPixelX ), - .OutPixelY ( OutPixelY ), - .OutR ( OutR ), - .OutG ( OutG ), - .OutB ( OutB ) + .OutEnable ( ColorEnable ), + .OutPixelX ( ColorPixelX ), + .OutPixelY ( ColorPixelY ), + .OutR ( ColorR ), + .OutG ( ColorG ), + .OutB ( ColorB ) ); - - reg ProcessIdle; - - // - always @(posedge clk or negedge rst) begin - if(!rst) begin - ProcessIdle <= 1'b1; - end else begin - if(JpegDecodeStart == 1'b1) ProcessIdle <= 1'b0; - else if(ProcessIdle <= 1'b0 & - OutWidth == OutPixelX -1 & - OutHeight == OutPixelY -1) ProcessIdle <= 1'b1; - end - end - assign JpegDecodeIdle = ProcessIdle; + // OutData + assign OutEnable = (ImageEnable)?ColorEnable:1'b0; + assign OutPixelX = (ImageEnable)?ColorPixelX:16'd0; + assign OutPixelY = (ImageEnable)?ColorPixelY:16'd0; + assign OutR = (ImageEnable)?ColorR:8'd0; + assign OutG = (ImageEnable)?ColorG:8'd0; + assign OutB = (ImageEnable)?ColorB:8'd0; endmodule // jpeg_decode 1.2 djpeg/src/jpeg_decode_fsm.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_decode_fsm.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_decode_fsm.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_decode_fsm.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_decode_fsm.v 5 Oct 2006 04:45:15 -0000 1.1 +++ jpeg_decode_fsm.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -7,14 +7,17 @@ // Author : H.Ishihara // E-Mail : hidemi@s... // HomePage : http://www.sweetcafe.jp/ -// Date : 2006/10/01 -// Rev. : 1.1 +// Date : 2007/04/11 +// Rev. : 1.03 //--------------------------------------------------------------------------- // Rev. Date Description //--------------------------------------------------------------------------- // 1.01 2006/10/01 1st Release // 1.02 2006/10/04 Remove a HmOldData register. // When reset, clear a ReadDqtTable register. +// 1.03 2007/04/11 Remove JpegDecodeStart +// Exchange StateMachine(Add ImageData) +// Remove JpegDecodeStart //--------------------------------------------------------------------------- // $Id: //--------------------------------------------------------------------------- @@ -29,12 +32,14 @@ DataInEnable, DataIn, - JpegDecodeStart, // JpegDecodeIdle, // Deocdeer Process Idle(1:Idle, 0:Run) OutWidth, OutHeight, OutBlockWidth, + OutEnable, + OutPixelX, + OutPixelY, // DqtEnable, @@ -71,12 +76,14 @@ input DataInEnable; input [31:0] DataIn; - input JpegDecodeStart; output JpegDecodeIdle; output [15:0] OutWidth; output [15:0] OutHeight; output [11:0] OutBlockWidth; + input OutEnable; + input [15:0] OutPixelX; + input [15:0] OutPixelY; output DqtEnable; output DqtTable; @@ -112,14 +119,14 @@ reg [3:0] Process; wire StateReadByte; wire StateReadWord; - reg ImageEnable; + wire ImageEnable; wire ReadSegmentEnd; parameter Idle = 2'b00; parameter GetMarker = 2'b01; parameter ReadSegment = 2'b10; - parameter EndOfDecode = 2'b11; + parameter ImageData = 2'b11; parameter NoProcess = 4'h0; parameter SegSOI = 4'h1; @@ -132,19 +139,20 @@ parameter SegRST = 4'h8; parameter SegEOI = 4'h9; + reg [15:0] JpegWidth; + reg [15:0] JpegHeight; + always @(posedge clk or negedge rst) begin if(!rst) begin State <= Idle; Process <= NoProcess; - ImageEnable <= 1'b0; end else begin - if(ImageEnable == 1'b0) begin case(State) Idle: begin - if(JpegDecodeStart == 1'b1) begin + if(DataInEnable == 1'b1) begin State <= GetMarker; end - ImageEnable <= 1'b0; + Process <= NoProcess; end GetMarker: begin if(DataInEnable == 1'b1) begin @@ -180,35 +188,36 @@ default: begin Process <= SegAPP; end - endcase // case(DataIn[31:16]) - end // if (DataInEnable == 1'b1) - end // case: GetMarker + endcase + end + end ReadSegment: begin if(ReadSegmentEnd == 1'b1) begin - State <= GetMarker; Process <= NoProcess; if(Process == SegSOS) begin - ImageEnable <= 1'b1; + State <= ImageData; + end else begin + State <= GetMarker; end end end - endcase // case(State) - end else if(ImageEnd == 1'b1) begin // if (ImageEnable == 1'b0) + ImageData: begin + if(OutEnable & (JpegWidth == OutPixelX +1) & (JpegHeight == OutPixelY +1)) begin State <= Idle; - ImageEnable <= 1'b0; end - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) + end + endcase + end + end - assign JpegDecodeIdle = State == Idle; + assign JpegDecodeIdle = (State == Idle); assign StateReadByte = 1'b0; - assign StateReadWord = State == GetMarker & DataInEnable == 1'b1 & - ImageEnable == 1'b0; - + assign StateReadWord = ((State == GetMarker) & (DataInEnable == 1'b1)); + assign ImageEnable = (State == ImageData); wire ReadNopEnd; - assign ReadNopEnd = Process == SegSOI | Process == SegRST; + assign ReadNopEnd = ((Process == SegSOI) | (Process == SegRST)); //-------------------------------------------------------------------------- // APP Segment @@ -221,19 +230,19 @@ wire ReadAppWord; wire ReadAppEnd; - parameter AppIdle = 2'b00; - parameter AppLength = 2'b01; - parameter AppRead = 2'b10; + parameter AppIdle = 2'd0; + parameter AppLength = 2'd1; + parameter AppRead = 2'd2; always @(posedge clk or negedge rst) begin if(!rst) begin StateAPP <= AppIdle; - ReadAppCount <= 16'h0000; + ReadAppCount <= 16'd0; end else begin case(StateAPP) AppIdle: begin if(Process == SegAPP) StateAPP <= AppLength; - ReadAppCount <= 16'h0000; + ReadAppCount <= 16'd0; end AppLength: begin if(DataInEnable == 1'b1) begin @@ -250,13 +259,12 @@ end end end - endcase // case(StateAPP) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - assign ReadAppByte = StateAPP == AppRead; - assign ReadAppWord = StateAPP == AppLength; - assign ReadAppEnd = StateAPP == AppRead & - DataInEnable == 1'b1 & ReadAppCount == 1; + endcase + end + end + assign ReadAppByte = (StateAPP == AppRead); + assign ReadAppWord = (StateAPP == AppLength); + assign ReadAppEnd = ((StateAPP == AppRead) & (DataInEnable == 1'b1) & (ReadAppCount == 1)); //-------------------------------------------------------------------------- // DQT Segment @@ -310,17 +318,16 @@ ReadDqtCount <= ReadDqtCount +1; end end - endcase // case(StateDQT) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) + endcase + end + end assign ReadDqtEnable = StateDQT == DQTRead; assign ReadDqtData = DataIn[31:24]; assign ReadDqtByte = StateDQT == DQTRead | StateDQT == DQTTable; assign ReadDqtWord = StateDQT == DQTLength; - assign ReadDqtEnd = StateDQT == DQTRead & - DataInEnable == 1'b1 & ReadDqtCount ==63; + assign ReadDqtEnd = StateDQT == DQTRead & DataInEnable == 1'b1 & ReadDqtCount ==63; //-------------------------------------------------------------------------- // DHT Segment @@ -381,7 +388,7 @@ 8'h10: ReadDhtTable <= 2'b01; 8'h01: ReadDhtTable <= 2'b10; 8'h11: ReadDhtTable <= 2'b11; - endcase // case(DataIn[31:24]) + endcase end HmShift <= 16'h8000; HmData <= 16'h0000; @@ -414,8 +421,8 @@ ReadDhtCount <= ReadDhtCount +1; end HmShift <= HmShift >> 1; - end // else: !if(HmCount != 0) - end // case: DHTMakeHm2 + end + end DHTReadTable: begin HmEnable <= 1'b0; if(DataInEnable == 1'b1) begin @@ -425,9 +432,9 @@ HmCount <= HmCount +1; end end - endcase // case(StateDHT) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) + endcase + end + end assign ReadDhtEnable = StateDHT == DHTReadTable; assign ReadDhtData = DataIn[31:24]; @@ -435,8 +442,7 @@ assign ReadDhtByte = StateDHT == DHTTable | StateDHT == DHTMakeHm0 | StateDHT == DHTReadTable; assign ReadDhtWord = StateDHT == DHTLength; - assign ReadDhtEnd = StateDHT == DHTReadTable & - DataInEnable == 1'b1 & HmMax == HmCount +1; + assign ReadDhtEnd = StateDHT == DHTReadTable & DataInEnable == 1'b1 & HmMax == HmCount +1; //-------------------------------------------------------------------------- // SOS Segment @@ -507,12 +513,10 @@ StateSOS <= SOSIdle; end end - endcase // case(StateSOS) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) - assign ReadSosByte = StateSOS == SOSRead0 | - StateSOS == SOSRead2 | StateSOS == SOSRead3 | - StateSOS == SOSRead4; + endcase + end + end + assign ReadSosByte = StateSOS == SOSRead0 | StateSOS == SOSRead2 | StateSOS == SOSRead3 | StateSOS == SOSRead4; assign ReadSosWord = StateSOS == SOSLength | StateSOS == SOSRead1; assign ReadSosEnd = DataInEnable == 1'b1 & StateSOS == SOSRead4; @@ -525,8 +529,6 @@ wire ReadSofWord; wire ReadSofEnd; - reg [15:0] JpegWidth; - reg [15:0] JpegHeight; reg [15:0] JpegBlockWidth; reg [15:0] JpegBlockHeight; @@ -600,12 +602,11 @@ JpegBlockWidth <= JpegBlockWidth >> 4; JpegBlockHeight <= JpegBlockHeight >> 4; end - endcase // case(StateSOF) - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) + endcase + end + end assign ReadSofByte = StateSOF == SOFRead0 | StateSOF == SOFReadComp; - assign ReadSofWord = StateSOF == SOFLength | StateSOF == SOFReadX | - StateSOF == SOFReadY ; + assign ReadSofWord = StateSOF == SOFLength | StateSOF == SOFReadX | StateSOF == SOFReadY ; assign ReadSofEnd = StateSOF == SOFMakeBlock1; assign OutWidth = JpegWidth; @@ -613,17 +614,9 @@ assign OutBlockWidth = JpegBlockWidth[11:0]; // - assign UseByte = DataInEnable == 1'b1 & - (StateReadByte | ReadAppByte | - ReadDqtByte | ReadDhtByte | - ReadSosByte | ReadSofByte) ; - assign UseWord = DataInEnable == 1'b1 & - (StateReadWord | ReadAppWord | - ReadDqtWord | ReadDhtWord | - ReadSosWord | ReadSofWord) ; - assign ReadSegmentEnd = ReadNopEnd | ReadAppEnd | - ReadDqtEnd | ReadDhtEnd | - ReadSosEnd | ReadSofEnd ; + assign UseByte = DataInEnable == 1'b1 & (StateReadByte | ReadAppByte | ReadDqtByte | ReadDhtByte | ReadSosByte | ReadSofByte) ; + assign UseWord = DataInEnable == 1'b1 & (StateReadWord | ReadAppWord | ReadDqtWord | ReadDhtWord | ReadSosWord | ReadSofWord) ; + assign ReadSegmentEnd = ReadNopEnd | ReadAppEnd | ReadDqtEnd | ReadDhtEnd | ReadSosEnd | ReadSofEnd ; // assign DqtEnable = ReadDqtEnable; @@ -644,4 +637,4 @@ assign HaffumanData = HmData; assign HaffumanStart = HmMax; -endmodule // jpeg_decode_fsm +endmodule 1.2 djpeg/src/jpeg_dht.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_dht.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_dht.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_dht.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_dht.v 5 Oct 2006 04:45:15 -0000 1.1 +++ jpeg_dht.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -58,7 +58,7 @@ reg [7:0] ReadDataCdc; reg [7:0] ReadDataCac; - reg [7:0] ReadData; + wire [7:0] ReadData; // RAM always @(posedge clk) begin @@ -84,6 +84,7 @@ end // always @ (posedge clk or negedge rst) // Selector +/* always @(*) begin case (ColorNumber) 2'b00: ReadData <= ReadDataYdc; @@ -92,6 +93,24 @@ 2'b11: ReadData <= ReadDataCac; endcase // case(ColorNumber) end +*/ + function [7:0] ReadDataSel; + input [1:0] ColorNumber; + input [7:0] ReadDataYdc; + input [7:0] ReadDataYac; + input [7:0] ReadDataCdc; + input [7:0] ReadDataCac; + begin + case (ColorNumber) + 2'b00: ReadDataSel = ReadDataYdc; + 2'b01: ReadDataSel = ReadDataYac; + 2'b10: ReadDataSel = ReadDataCdc; + 2'b11: ReadDataSel = ReadDataCac; + endcase + end + endfunction + + assign ReadData = ReadDataSel(ColorNumber, ReadDataYdc, ReadDataYac, ReadDataCdc, ReadDataCac); assign ZeroTable = ReadData[7:4]; assign WidhtTable = ReadData[3:0]; 1.2 djpeg/src/jpeg_hm_decode.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_hm_decode.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_hm_decode.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_hm_decode.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_hm_decode.v 5 Oct 2006 04:45:15 -0000 1.1 +++ jpeg_hm_decode.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -117,7 +117,6 @@ always @(posedge clk or negedge rst) begin if(!rst) begin - for(i=0;i<16;i=i+1) begin HaffumanTable0r[0] <= 16'h0000; HaffumanNumber0r[0] <= 8'h00; HaffumanTable1r[0] <= 16'h0000; @@ -126,7 +125,141 @@ HaffumanNumber2r[0] <= 8'h00; HaffumanTable3r[0] <= 16'h0000; HaffumanNumber3r[0] <= 8'h00; - end + + HaffumanTable0r[1] <= 16'h0000; + HaffumanNumber0r[1] <= 8'h00; + HaffumanTable1r[1] <= 16'h0000; + HaffumanNumber1r[1] <= 8'h00; + HaffumanTable2r[1] <= 16'h0000; + HaffumanNumber2r[1] <= 8'h00; + HaffumanTable3r[1] <= 16'h0000; + HaffumanNumber3r[1] <= 8'h00; + + HaffumanTable0r[2] <= 16'h0000; + HaffumanNumber0r[2] <= 8'h00; + HaffumanTable1r[2] <= 16'h0000; + HaffumanNumber1r[2] <= 8'h00; + HaffumanTable2r[2] <= 16'h0000; + HaffumanNumber2r[2] <= 8'h00; + HaffumanTable3r[2] <= 16'h0000; + HaffumanNumber3r[2] <= 8'h00; + + HaffumanTable0r[3] <= 16'h0000; + HaffumanNumber0r[3] <= 8'h00; + HaffumanTable1r[3] <= 16'h0000; + HaffumanNumber1r[3] <= 8'h00; + HaffumanTable2r[3] <= 16'h0000; + HaffumanNumber2r[3] <= 8'h00; + HaffumanTable3r[3] <= 16'h0000; + HaffumanNumber3r[3] <= 8'h00; + + HaffumanTable0r[4] <= 16'h0000; + HaffumanNumber0r[4] <= 8'h00; + HaffumanTable1r[4] <= 16'h0000; + HaffumanNumber1r[4] <= 8'h00; + HaffumanTable2r[4] <= 16'h0000; + HaffumanNumber2r[4] <= 8'h00; + HaffumanTable3r[4] <= 16'h0000; + HaffumanNumber3r[4] <= 8'h00; + + HaffumanTable0r[5] <= 16'h0000; + HaffumanNumber0r[5] <= 8'h00; + HaffumanTable1r[5] <= 16'h0000; + HaffumanNumber1r[5] <= 8'h00; + HaffumanTable2r[5] <= 16'h0000; + HaffumanNumber2r[5] <= 8'h00; + HaffumanTable3r[5] <= 16'h0000; + HaffumanNumber3r[5] <= 8'h00; + + HaffumanTable0r[6] <= 16'h0000; + HaffumanNumber0r[6] <= 8'h00; + HaffumanTable1r[6] <= 16'h0000; + HaffumanNumber1r[6] <= 8'h00; + HaffumanTable2r[6] <= 16'h0000; + HaffumanNumber2r[6] <= 8'h00; + HaffumanTable3r[6] <= 16'h0000; + HaffumanNumber3r[6] <= 8'h00; + + HaffumanTable0r[7] <= 16'h0000; + HaffumanNumber0r[7] <= 8'h00; + HaffumanTable1r[7] <= 16'h0000; + HaffumanNumber1r[7] <= 8'h00; + HaffumanTable2r[7] <= 16'h0000; + HaffumanNumber2r[7] <= 8'h00; + HaffumanTable3r[7] <= 16'h0000; + HaffumanNumber3r[7] <= 8'h00; + + HaffumanTable0r[8] <= 16'h0000; + HaffumanNumber0r[8] <= 8'h00; + HaffumanTable1r[8] <= 16'h0000; + HaffumanNumber1r[8] <= 8'h00; + HaffumanTable2r[8] <= 16'h0000; + HaffumanNumber2r[8] <= 8'h00; + HaffumanTable3r[8] <= 16'h0000; + HaffumanNumber3r[8] <= 8'h00; + + HaffumanTable0r[9] <= 16'h0000; + HaffumanNumber0r[9] <= 8'h00; + HaffumanTable1r[9] <= 16'h0000; + HaffumanNumber1r[9] <= 8'h00; + HaffumanTable2r[9] <= 16'h0000; + HaffumanNumber2r[9] <= 8'h00; + HaffumanTable3r[9] <= 16'h0000; + HaffumanNumber3r[9] <= 8'h00; + + HaffumanTable0r[10] <= 16'h0000; + HaffumanNumber0r[10] <= 8'h00; + HaffumanTable1r[10] <= 16'h0000; + HaffumanNumber1r[10] <= 8'h00; + HaffumanTable2r[10] <= 16'h0000; + HaffumanNumber2r[10] <= 8'h00; + HaffumanTable3r[10] <= 16'h0000; + HaffumanNumber3r[10] <= 8'h00; + + HaffumanTable0r[11] <= 16'h0000; + HaffumanNumber0r[11] <= 8'h00; + HaffumanTable1r[11] <= 16'h0000; + HaffumanNumber1r[11] <= 8'h00; + HaffumanTable2r[11] <= 16'h0000; + HaffumanNumber2r[11] <= 8'h00; + HaffumanTable3r[11] <= 16'h0000; + HaffumanNumber3r[11] <= 8'h00; + + HaffumanTable0r[12] <= 16'h0000; + HaffumanNumber0r[12] <= 8'h00; + HaffumanTable1r[12] <= 16'h0000; + HaffumanNumber1r[12] <= 8'h00; + HaffumanTable2r[12] <= 16'h0000; + HaffumanNumber2r[12] <= 8'h00; + HaffumanTable3r[12] <= 16'h0000; + HaffumanNumber3r[12] <= 8'h00; + + HaffumanTable0r[13] <= 16'h0000; + HaffumanNumber0r[13] <= 8'h00; + HaffumanTable1r[13] <= 16'h0000; + HaffumanNumber1r[13] <= 8'h00; + HaffumanTable2r[13] <= 16'h0000; + HaffumanNumber2r[13] <= 8'h00; + HaffumanTable3r[13] <= 16'h0000; + HaffumanNumber3r[13] <= 8'h00; + + HaffumanTable0r[14] <= 16'h0000; + HaffumanNumber0r[14] <= 8'h00; + HaffumanTable1r[14] <= 16'h0000; + HaffumanNumber1r[14] <= 8'h00; + HaffumanTable2r[14] <= 16'h0000; + HaffumanNumber2r[14] <= 8'h00; + HaffumanTable3r[14] <= 16'h0000; + HaffumanNumber3r[14] <= 8'h00; + + HaffumanTable0r[15] <= 16'h0000; + HaffumanNumber0r[15] <= 8'h00; + HaffumanTable1r[15] <= 16'h0000; + HaffumanNumber1r[15] <= 8'h00; + HaffumanTable2r[15] <= 16'h0000; + HaffumanNumber2r[15] <= 8'h00; + HaffumanTable3r[15] <= 16'h0000; + HaffumanNumber3r[15] <= 8'h00; end else begin // if (!rst) if(HaffumanTableEnable ==2'b1) begin if(HaffumanTableColor ==2'b00) begin @@ -173,7 +306,7 @@ reg OutEnable; // Output Enable reg [3:0] OutZero; // Output Zero Count reg [15:0] OutCode; // Output Data Code - reg [15:0] OutCodeP; // Output Data Code + wire [15:0] OutCodeP; // Output Data Code reg [4:0] UseWidth; // Output used width @@ -184,7 +317,7 @@ reg signed [31:0] PreData [0:2]; - reg [15:0] SubCode; + wire [15:0] SubCode; parameter ProcIdle = 4'h0; parameter Phase1 = 4'h1; @@ -199,6 +332,7 @@ parameter Phase10 = 4'hA; parameter Phase11 = 4'hB; +/* always @(*) begin case (DhtWidth) 4'h0: OutCodeP <= 16'h0000; @@ -237,7 +371,58 @@ 4'hF: SubCode <= 16'h8000; endcase // case(DhtWidth) end // always @ (*) +*/ + + function [15:0] OutCodePSel; + input [3:0] DhtWidth; + input [31:0] ProcessData; + begin + case (DhtWidth) + 4'h0: OutCodePSel = 16'h0000; + 4'h1: OutCodePSel = {15'h0000,ProcessData[31]}; + 4'h2: OutCodePSel = {14'h0000,ProcessData[31:30]}; + 4'h3: OutCodePSel = {13'h0000,ProcessData[31:29]}; + 4'h4: OutCodePSel = {12'h000, ProcessData[31:28]}; + 4'h5: OutCodePSel = {11'h000, ProcessData[31:27]}; + 4'h6: OutCodePSel = {10'h000, ProcessData[31:26]}; + 4'h7: OutCodePSel = {9'h000, ProcessData[31:25]}; + 4'h8: OutCodePSel = {8'h00, ProcessData[31:24]}; + 4'h9: OutCodePSel = {7'h00, ProcessData[31:23]}; + 4'hA: OutCodePSel = {6'h00, ProcessData[31:22]}; + 4'hB: OutCodePSel = {5'h00, ProcessData[31:21]}; + 4'hC: OutCodePSel = {4'h0, ProcessData[31:20]}; + 4'hD: OutCodePSel = {3'h0, ProcessData[31:19]}; + 4'hE: OutCodePSel = {2'h0, ProcessData[31:18]}; + 4'hF: OutCodePSel = {1'h0, ProcessData[31:17]}; + endcase // case(DhtWidth) + end + endfunction + assign OutCodeP = OutCodePSel(DhtWidth, ProcessData); + function [15:0] SubCodeSel; + input [3:0] DhtWidth; + begin + case (DhtWidth) + 4'h0: SubCodeSel = 16'hFFFF; + 4'h1: SubCodeSel = 16'hFFFE; + 4'h2: SubCodeSel = 16'hFFFC; + 4'h3: SubCodeSel = 16'hFFF8; + 4'h4: SubCodeSel = 16'hFFF0; + 4'h5: SubCodeSel = 16'hFFE0; + 4'h6: SubCodeSel = 16'hFFC0; + 4'h7: SubCodeSel = 16'hFF80; + 4'h8: SubCodeSel = 16'hFF00; + 4'h9: SubCodeSel = 16'hFE00; + 4'hA: SubCodeSel = 16'hFC00; + 4'hB: SubCodeSel = 16'hF800; + 4'hC: SubCodeSel = 16'hF000; + 4'hD: SubCodeSel = 16'hE000; + 4'hE: SubCodeSel = 16'hC000; + 4'hF: SubCodeSel = 16'h8000; + endcase // case(DhtWidth) + end + endfunction + assign SubCode = SubCodeSel(DhtWidth); always @(posedge clk or negedge rst) begin if(!rst) begin @@ -250,6 +435,7 @@ PreData[1] <= 32'h00000000; PreData[2] <= 32'h00000000; UseWidth <= 7'h00; + CodeNumber <= 4'd0; end else begin // if (!rst) case (Process) ProcIdle: begin @@ -277,39 +463,177 @@ DataOutEnable <= 1'b0; if(ProcessColor[2] == 1'b0) begin if(ProcessCount == 0) begin - for(i=0;i<16;i=i+1) begin - HaffumanTable[i] <= HaffumanTable0r[i]; - HaffumanNumber[i] <= HaffumanNumber0r[i]; - end - end else begin - for(i=0;i<16;i=i+1) begin - HaffumanTable[i] <= HaffumanTable1r[i]; - HaffumanNumber[i] <= HaffumanNumber1r[i]; - end + HaffumanTable[0] <= HaffumanTable0r[0]; + HaffumanNumber[0] <= HaffumanNumber0r[0]; + HaffumanTable[1] <= HaffumanTable0r[1]; + HaffumanNumber[1] <= HaffumanNumber0r[1]; + HaffumanTable[2] <= HaffumanTable0r[2]; + HaffumanNumber[2] <= HaffumanNumber0r[2]; + HaffumanTable[3] <= HaffumanTable0r[3]; + HaffumanNumber[3] <= HaffumanNumber0r[3]; + HaffumanTable[4] <= HaffumanTable0r[4]; + HaffumanNumber[4] <= HaffumanNumber0r[4]; + HaffumanTable[5] <= HaffumanTable0r[5]; + HaffumanNumber[5] <= HaffumanNumber0r[5]; + HaffumanTable[6] <= HaffumanTable0r[6]; + HaffumanNumber[6] <= HaffumanNumber0r[6]; + HaffumanTable[7] <= HaffumanTable0r[7]; + HaffumanNumber[7] <= HaffumanNumber0r[7]; + HaffumanTable[8] <= HaffumanTable0r[8]; + HaffumanNumber[8] <= HaffumanNumber0r[8]; + HaffumanTable[9] <= HaffumanTable0r[9]; + HaffumanNumber[9] <= HaffumanNumber0r[9]; + HaffumanTable[10] <= HaffumanTable0r[10]; + HaffumanNumber[10] <= HaffumanNumber0r[10]; + HaffumanTable[11] <= HaffumanTable0r[11]; + HaffumanNumber[11] <= HaffumanNumber0r[11]; + HaffumanTable[12] <= HaffumanTable0r[12]; + HaffumanNumber[12] <= HaffumanNumber0r[12]; + HaffumanTable[13] <= HaffumanTable0r[13]; + HaffumanNumber[13] <= HaffumanNumber0r[13]; + HaffumanTable[14] <= HaffumanTable0r[14]; + HaffumanNumber[14] <= HaffumanNumber0r[14]; + HaffumanTable[15] <= HaffumanTable0r[15]; + HaffumanNumber[15] <= HaffumanNumber0r[15]; + end else begin + HaffumanTable[0] <= HaffumanTable1r[0]; + HaffumanNumber[0] <= HaffumanNumber1r[0]; + HaffumanTable[1] <= HaffumanTable1r[1]; + HaffumanNumber[1] <= HaffumanNumber1r[1]; + HaffumanTable[2] <= HaffumanTable1r[2]; + HaffumanNumber[2] <= HaffumanNumber1r[2]; + HaffumanTable[3] <= HaffumanTable1r[3]; + HaffumanNumber[3] <= HaffumanNumber1r[3]; + HaffumanTable[4] <= HaffumanTable1r[4]; + HaffumanNumber[4] <= HaffumanNumber1r[4]; + HaffumanTable[5] <= HaffumanTable1r[5]; + HaffumanNumber[5] <= HaffumanNumber1r[5]; + HaffumanTable[6] <= HaffumanTable1r[6]; + HaffumanNumber[6] <= HaffumanNumber1r[6]; + HaffumanTable[7] <= HaffumanTable1r[7]; + HaffumanNumber[7] <= HaffumanNumber1r[7]; + HaffumanTable[8] <= HaffumanTable1r[8]; + HaffumanNumber[8] <= HaffumanNumber1r[8]; + HaffumanTable[9] <= HaffumanTable1r[9]; + HaffumanNumber[9] <= HaffumanNumber1r[9]; + HaffumanTable[10] <= HaffumanTable1r[10]; + HaffumanNumber[10] <= HaffumanNumber1r[10]; + HaffumanTable[11] <= HaffumanTable1r[11]; + HaffumanNumber[11] <= HaffumanNumber1r[11]; + HaffumanTable[12] <= HaffumanTable1r[12]; + HaffumanNumber[12] <= HaffumanNumber1r[12]; + HaffumanTable[13] <= HaffumanTable1r[13]; + HaffumanNumber[13] <= HaffumanNumber1r[13]; + HaffumanTable[14] <= HaffumanTable1r[14]; + HaffumanNumber[14] <= HaffumanNumber1r[14]; + HaffumanTable[15] <= HaffumanTable1r[15]; + HaffumanNumber[15] <= HaffumanNumber1r[15]; end // else: !if(ProcessCount == 0) end else begin // if (ProcessColor[2] == 1'b0) if(ProcessCount == 0) begin - for(i=0;i<16;i=i+1) begin - HaffumanTable[i] <= HaffumanTable2r[i]; - HaffumanNumber[i] <= HaffumanNumber2r[i]; - end - end else begin - for(i=0;i<16;i=i+1) begin - HaffumanTable[i] <= HaffumanTable3r[i]; - HaffumanNumber[i] <= HaffumanNumber3r[i]; - end + HaffumanTable[0] <= HaffumanTable2r[0]; + HaffumanNumber[0] <= HaffumanNumber2r[0]; + HaffumanTable[1] <= HaffumanTable2r[1]; + HaffumanNumber[1] <= HaffumanNumber2r[1]; + HaffumanTable[2] <= HaffumanTable2r[2]; + HaffumanNumber[2] <= HaffumanNumber2r[2]; + HaffumanTable[3] <= HaffumanTable2r[3]; + HaffumanNumber[3] <= HaffumanNumber2r[3]; + HaffumanTable[4] <= HaffumanTable2r[4]; + HaffumanNumber[4] <= HaffumanNumber2r[4]; + HaffumanTable[5] <= HaffumanTable2r[5]; + HaffumanNumber[5] <= HaffumanNumber2r[5]; + HaffumanTable[6] <= HaffumanTable2r[6]; + HaffumanNumber[6] <= HaffumanNumber2r[6]; + HaffumanTable[7] <= HaffumanTable2r[7]; + HaffumanNumber[7] <= HaffumanNumber2r[7]; + HaffumanTable[8] <= HaffumanTable2r[8]; + HaffumanNumber[8] <= HaffumanNumber2r[8]; + HaffumanTable[9] <= HaffumanTable2r[9]; + HaffumanNumber[9] <= HaffumanNumber2r[9]; + HaffumanTable[10] <= HaffumanTable2r[10]; + HaffumanNumber[10] <= HaffumanNumber2r[10]; + HaffumanTable[11] <= HaffumanTable2r[11]; + HaffumanNumber[11] <= HaffumanNumber2r[11]; + HaffumanTable[12] <= HaffumanTable2r[12]; + HaffumanNumber[12] <= HaffumanNumber2r[12]; + HaffumanTable[13] <= HaffumanTable2r[13]; + HaffumanNumber[13] <= HaffumanNumber2r[13]; + HaffumanTable[14] <= HaffumanTable2r[14]; + HaffumanNumber[14] <= HaffumanNumber2r[14]; + HaffumanTable[15] <= HaffumanTable2r[15]; + HaffumanNumber[15] <= HaffumanNumber2r[15]; + end else begin + HaffumanTable[0] <= HaffumanTable3r[0]; + HaffumanNumber[0] <= HaffumanNumber3r[0]; + HaffumanTable[1] <= HaffumanTable3r[1]; + HaffumanNumber[1] <= HaffumanNumber3r[1]; + HaffumanTable[2] <= HaffumanTable3r[2]; + HaffumanNumber[2] <= HaffumanNumber3r[2]; + HaffumanTable[3] <= HaffumanTable3r[3]; + HaffumanNumber[3] <= HaffumanNumber3r[3]; + HaffumanTable[4] <= HaffumanTable3r[4]; + HaffumanNumber[4] <= HaffumanNumber3r[4]; + HaffumanTable[5] <= HaffumanTable3r[5]; + HaffumanNumber[5] <= HaffumanNumber3r[5]; + HaffumanTable[6] <= HaffumanTable3r[6]; + HaffumanNumber[6] <= HaffumanNumber3r[6]; + HaffumanTable[7] <= HaffumanTable3r[7]; + HaffumanNumber[7] <= HaffumanNumber3r[7]; + HaffumanTable[8] <= HaffumanTable3r[8]; + HaffumanNumber[8] <= HaffumanNumber3r[8]; + HaffumanTable[9] <= HaffumanTable3r[9]; + HaffumanNumber[9] <= HaffumanNumber3r[9]; + HaffumanTable[10] <= HaffumanTable3r[10]; + HaffumanNumber[10] <= HaffumanNumber3r[10]; + HaffumanTable[11] <= HaffumanTable3r[11]; + HaffumanNumber[11] <= HaffumanNumber3r[11]; + HaffumanTable[12] <= HaffumanTable3r[12]; + HaffumanNumber[12] <= HaffumanNumber3r[12]; + HaffumanTable[13] <= HaffumanTable3r[13]; + HaffumanNumber[13] <= HaffumanNumber3r[13]; + HaffumanTable[14] <= HaffumanTable3r[14]; + HaffumanNumber[14] <= HaffumanNumber3r[14]; + HaffumanTable[15] <= HaffumanTable3r[15]; + HaffumanNumber[15] <= HaffumanNumber3r[15]; end // else: !if(ProcessCount == 0) end // else: !if(ProcessColor[2] == 1'b0) end // case: Phase1 // compare table Phase2: begin Process <= Phase4; - for(i=0;i<16;i=i+1) begin - if(ProcessData[31:16] >= HaffumanTable[i]) - Place[i] <= 1'b1; - else - Place[i] <= 1'b0; - end + if(ProcessData[31:16] >= HaffumanTable[0]) Place[0] <= 1'b1; + else Place[0] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[1]) Place[1] <= 1'b1; + else Place[1] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[2]) Place[2] <= 1'b1; + else Place[2] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[3]) Place[3] <= 1'b1; + else Place[3] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[4]) Place[4] <= 1'b1; + else Place[4] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[5]) Place[5] <= 1'b1; + else Place[5] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[6]) Place[6] <= 1'b1; + else Place[6] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[7]) Place[7] <= 1'b1; + else Place[7] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[8]) Place[8] <= 1'b1; + else Place[8] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[9]) Place[9] <= 1'b1; + else Place[9] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[10]) Place[10] <= 1'b1; + else Place[10] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[11]) Place[11] <= 1'b1; + else Place[11] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[12]) Place[12] <= 1'b1; + else Place[12] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[13]) Place[13] <= 1'b1; + else Place[13] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[14]) Place[14] <= 1'b1; + else Place[14] <= 1'b0; + if(ProcessData[31:16] >= HaffumanTable[15]) Place[15] <= 1'b1; + else Place[15] <= 1'b0; end // shift code Phase4: begin 1.2 djpeg/src/jpeg_idctx.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_idctx.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_idctx.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_idctx.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_idctx.v 5 Oct 2006 04:45:15 -0000 1.1 +++ jpeg_idctx.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -230,13 +230,14 @@ assign DataInIdle = Phase1Enable == 1'b0 & DataOutIdle == 1'b1; assign DataInRelease = Phase1Enable == 1'b1 & Phase1Count == 3'd6 & Phase1Page == 3'd7; - reg signed [15:0] Phase1R0w; - reg signed [15:0] Phase1R1w; - reg signed [15:0] Phase1C0w; - reg signed [15:0] Phase1C1w; - reg signed [15:0] Phase1C2w; - reg signed [15:0] Phase1C3w; + wire signed [15:0] Phase1R0w; + wire signed [15:0] Phase1R1w; + wire signed [15:0] Phase1C0w; + wire signed [15:0] Phase1C1w; + wire signed [15:0] Phase1C2w; + wire signed [15:0] Phase1C3w; +/* always @(*) begin case(Phase1Page) 3'd0:begin @@ -401,7 +402,427 @@ end // case: 3'd7 endcase // case(Phase1Page) end // always @ (*) +*/ + function [15:0] Phase1R0wSel; + input [2:0] Phase1Page; + input [2:0] Phase1Count; + input [15:0] Data00In; + input [15:0] Data01In; + input [15:0] Data02In; + input [15:0] Data03In; + input [15:0] Data04In; + input [15:0] Data05In; + input [15:0] Data06In; + input [15:0] Data07In; + input [15:0] Data08In; + input [15:0] Data09In; + input [15:0] Data10In; + input [15:0] Data11In; + input [15:0] Data12In; + input [15:0] Data13In; + input [15:0] Data14In; + input [15:0] Data15In; + input [15:0] Data16In; + input [15:0] Data17In; + input [15:0] Data18In; + input [15:0] Data19In; + input [15:0] Data20In; + input [15:0] Data21In; + input [15:0] Data22In; + input [15:0] Data23In; + input [15:0] Data24In; + input [15:0] Data25In; + input [15:0] Data26In; + input [15:0] Data27In; + input [15:0] Data28In; + input [15:0] Data29In; + input [15:0] Data30In; + input [15:0] Data31In; + input [15:0] Data32In; + input [15:0] Data33In; + input [15:0] Data34In; + input [15:0] Data35In; + input [15:0] Data36In; + input [15:0] Data37In; + input [15:0] Data38In; + input [15:0] Data39In; + input [15:0] Data40In; + input [15:0] Data41In; + input [15:0] Data42In; + input [15:0] Data43In; + input [15:0] Data44In; + input [15:0] Data45In; + input [15:0] Data46In; + input [15:0] Data47In; + input [15:0] Data48In; + input [15:0] Data49In; + input [15:0] Data50In; + input [15:0] Data51In; + input [15:0] Data52In; + input [15:0] Data53In; + input [15:0] Data54In; + input [15:0] Data55In; + input [15:0] Data56In; + input [15:0] Data57In; + input [15:0] Data58In; + input [15:0] Data59In; + input [15:0] Data60In; + input [15:0] Data61In; + input [15:0] Data62In; + input [15:0] Data63In; + begin + case(Phase1Page) + 3'd0:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data00In; + end + 3'd1: begin + Phase1R0wSel = Data02In; + end + 3'd2: begin + Phase1R0wSel = Data01In; + end + 3'd3: begin + Phase1R0wSel = Data05In; + end + endcase // case(Phase1Count) + end // case: 3'd0 + 3'd1:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data08In; + end + 3'd1: begin + Phase1R0wSel = Data10In; + end + 3'd2: begin + Phase1R0wSel = Data09In; + end + 3'd3: begin + Phase1R0wSel = Data13In; + end + endcase // case(Phase1Count) + end // case: 3'd1 + 3'd2:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data16In; + end + 3'd1: begin + Phase1R0wSel = Data18In; + end + 3'd2: begin + Phase1R0wSel = Data17In; + end + 3'd3: begin + Phase1R0wSel = Data21In; + end + endcase // case(Phase1Count) + end // case: 3'd2 + 3'd3:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data24In; + end + 3'd1: begin + Phase1R0wSel = Data26In; + end + 3'd2: begin + Phase1R0wSel = Data25In; + end + 3'd3: begin + Phase1R0wSel = Data29In; + end + endcase // case(Phase1Count) + end // case: 3'd3 + 3'd4:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data32In; + end + 3'd1: begin + Phase1R0wSel = Data34In; + end + 3'd2: begin + Phase1R0wSel = Data33In; + end + 3'd3: begin + Phase1R0wSel = Data37In; + end + endcase // case(Phase1Count) + end // case: 3'd4 + 3'd5:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data40In; + end + 3'd1: begin + Phase1R0wSel = Data42In; + end + 3'd2: begin + Phase1R0wSel = Data41In; + end + 3'd3: begin + Phase1R0wSel = Data45In; + end + endcase // case(Phase1Count) + end // case: 3'd5 + 3'd6:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data48In; + end + 3'd1: begin + Phase1R0wSel = Data50In; + end + 3'd2: begin + Phase1R0wSel = Data49In; + end + 3'd3: begin + Phase1R0wSel = Data53In; + end + endcase // case(Phase1Count) + end // case: 3'd6 + 3'd7:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data56In; + end + 3'd1: begin + Phase1R0wSel = Data58In; + end + 3'd2: begin + Phase1R0wSel = Data57In; + end + 3'd3: begin + Phase1R0wSel = Data61In; + end + endcase // case(Phase1Count) + end // case: 3'd7 + endcase // case(Phase1Page) + end + endfunction + function [15:0] Phase1R1wSel; + input [2:0] Phase1Page; + input [2:0] Phase1Count; + input [15:0] Data00In; + input [15:0] Data01In; + input [15:0] Data02In; + input [15:0] Data03In; + input [15:0] Data04In; + input [15:0] Data05In; + input [15:0] Data06In; + input [15:0] Data07In; + input [15:0] Data08In; + input [15:0] Data09In; + input [15:0] Data10In; + input [15:0] Data11In; + input [15:0] Data12In; + input [15:0] Data13In; + input [15:0] Data14In; + input [15:0] Data15In; + input [15:0] Data16In; + input [15:0] Data17In; + input [15:0] Data18In; + input [15:0] Data19In; + input [15:0] Data20In; + input [15:0] Data21In; + input [15:0] Data22In; + input [15:0] Data23In; + input [15:0] Data24In; + input [15:0] Data25In; + input [15:0] Data26In; + input [15:0] Data27In; + input [15:0] Data28In; + input [15:0] Data29In; + input [15:0] Data30In; + input [15:0] Data31In; + input [15:0] Data32In; + input [15:0] Data33In; + input [15:0] Data34In; + input [15:0] Data35In; + input [15:0] Data36In; + input [15:0] Data37In; + input [15:0] Data38In; + input [15:0] Data39In; + input [15:0] Data40In; + input [15:0] Data41In; + input [15:0] Data42In; + input [15:0] Data43In; + input [15:0] Data44In; + input [15:0] Data45In; + input [15:0] Data46In; + input [15:0] Data47In; + input [15:0] Data48In; + input [15:0] Data49In; + input [15:0] Data50In; + input [15:0] Data51In; + input [15:0] Data52In; + input [15:0] Data53In; + input [15:0] Data54In; + input [15:0] Data55In; + input [15:0] Data56In; + input [15:0] Data57In; + input [15:0] Data58In; + input [15:0] Data59In; + input [15:0] Data60In; + input [15:0] Data61In; + input [15:0] Data62In; + input [15:0] Data63In; + begin + case(Phase1Page) + 3'd0:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data04In; + end + 3'd1: begin + Phase1R1wSel = Data06In; + end + 3'd2: begin + Phase1R1wSel = Data07In; + end + 3'd3: begin + Phase1R1wSel = Data03In; + end + endcase // case(Phase1Count) + end // case: 3'd0 + 3'd1:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data12In; + end + 3'd1: begin + Phase1R1wSel = Data14In; + end + 3'd2: begin + Phase1R1wSel = Data15In; + end + 3'd3: begin + Phase1R1wSel = Data11In; + end + endcase // case(Phase1Count) + end // case: 3'd1 + 3'd2:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data20In; + end + 3'd1: begin + Phase1R1wSel = Data22In; + end + 3'd2: begin + Phase1R1wSel = Data23In; + end + 3'd3: begin + Phase1R1wSel = Data19In; + end + endcase // case(Phase1Count) + end // case: 3'd2 + 3'd3:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data28In; + end + 3'd1: begin + Phase1R1wSel = Data30In; + end + 3'd2: begin + Phase1R1wSel = Data31In; + end + 3'd3: begin + Phase1R1wSel = Data27In; + end + endcase // case(Phase1Count) + end // case: 3'd3 + 3'd4:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data36In; + end + 3'd1: begin + Phase1R1wSel = Data38In; + end + 3'd2: begin + Phase1R1wSel = Data39In; + end + 3'd3: begin + Phase1R1wSel = Data35In; + end + endcase // case(Phase1Count) + end // case: 3'd4 + 3'd5:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data44In; + end + 3'd1: begin + Phase1R1wSel = Data46In; + end + 3'd2: begin + Phase1R1wSel = Data47In; + end + 3'd3: begin + Phase1R1wSel = Data43In; + end + endcase // case(Phase1Count) + end // case: 3'd5 + 3'd6:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data52In; + end + 3'd1: begin + Phase1R1wSel = Data54In; + end + 3'd2: begin + Phase1R1wSel = Data55In; + end + 3'd3: begin + Phase1R1wSel = Data51In; + end + endcase // case(Phase1Count) + end // case: 3'd6 + 3'd7:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data60In; + end + 3'd1: begin + Phase1R1wSel = Data62In; + end + 3'd2: begin + Phase1R1wSel = Data63In; + end + 3'd3: begin + Phase1R1wSel = Data59In; + end + endcase // case(Phase1Count) + end // case: 3'd7 + endcase // case(Phase1Page) + end + endfunction + assign Phase1R0w = Phase1R0wSel(Phase1Page, Phase1Count, + Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In, + Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In, + Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In, + Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In, + Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In, + Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In, + Data60In, Data61In, Data62In, Data63In + ); + assign Phase1R1w = Phase1R1wSel(Phase1Page, Phase1Count, + Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In, + Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In, + Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In, + Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In, + Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In, + Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In, + Data60In, Data61In, Data62In, Data63In + ); +/* always @(*) begin case(Phase1Count) 3'd0: begin @@ -428,10 +849,93 @@ Phase1C2w <= 16'd3406; // C3_16 Phase1C3w <= 16'd2276; // C5_16 end + endcase // case(Phase1Count) + end // always @ (*) +*/ + function [15:0] Phase1C0wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C0wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C0wSel = 16'd3784; // C2_16 + end + 3'd2: begin + Phase1C0wSel = 16'd4017; // C1_16 + end + 3'd3: begin + Phase1C0wSel = 16'd2276; // C5_16 + end + endcase // case(Phase1Count) + end + endfunction + + function [15:0] Phase1C1wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C1wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C1wSel = 16'd1567; // C6_16 + end + 3'd2: begin + Phase1C1wSel = 16'd799; // C7_16 + end + 3'd3: begin + Phase1C1wSel = 16'd3406; // C3_16 + end + endcase // case(Phase1Count) + end + endfunction + function [15:0] Phase1C2wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C2wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C2wSel = 16'd1567; // C6_16 + end + 3'd2: begin + Phase1C2wSel = 16'd799; // C7_16 + end + 3'd3: begin + Phase1C2wSel = 16'd3406; // C3_16 + end endcase // case(Phase1Count) + end + endfunction - end // always @ (*) + function [15:0] Phase1C3wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C3wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C3wSel = 16'd3784; // C2_16 + end + 3'd2: begin + Phase1C3wSel = 16'd4017; // C1_16 + end + 3'd3: begin + Phase1C3wSel = 16'd2276; // C5_16 + end + endcase // case(Phase1Count) + end + endfunction + + assign Phase1C0w = Phase1C0wSel(Phase1Count); + assign Phase1C1w = Phase1C1wSel(Phase1Count); + assign Phase1C2w = Phase1C2wSel(Phase1Count); + assign Phase1C3w = Phase1C3wSel(Phase1Count); reg signed [31:0] Phase1R0r; reg signed [31:0] Phase1R1r; @@ -482,13 +986,16 @@ end // else: !if(!rst) end // always @ (posedge clk or negedge rst) - reg signed [31:0] Phase2A0w; - reg signed [31:0] Phase2A1w; - + wire signed [31:0] Phase2A0w; + wire signed [31:0] Phase2A1w; +/* always @(*) begin Phase2A0w <= Phase1R0r + Phase1R1r; Phase2A1w <= Phase1R2r - Phase1R3r; end +*/ + assign Phase2A0w = Phase1R0r + Phase1R1r; + assign Phase2A1w = Phase1R2r - Phase1R3r; reg signed [31:0] Phase2Reg [0:7]; @@ -572,13 +1079,16 @@ - reg signed [31:0] Phase3A0w; - reg signed [31:0] Phase3A1w; - + wire signed [31:0] Phase3A0w; + wire signed [31:0] Phase3A1w; +/* always @(*) begin Phase3A0w <= Phase3R0w + Phase3R1w; Phase3A1w <= Phase3R0w - Phase3R1w; end +*/ + assign Phase3A0w = Phase3R0w + Phase3R1w; + assign Phase3A1w = Phase3R0w - Phase3R1w; reg signed [31:0] Phase3Reg [0:7]; 1.2 djpeg/src/jpeg_idcty.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_idcty.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_idcty.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_idcty.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_idcty.v 5 Oct 2006 04:45:15 -0000 1.1 +++ jpeg_idcty.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -230,13 +230,13 @@ assign DataInIdle = Phase1Enable == 1'b0; assign DataInRelease = Phase1Enable == 1'b1 & Phase1Count == 3'd6 & Phase1Page == 3'd7; - reg signed [15:0] Phase1R0w; - reg signed [15:0] Phase1R1w; - reg signed [15:0] Phase1C0w; - reg signed [15:0] Phase1C1w; - reg signed [15:0] Phase1C2w; - reg signed [15:0] Phase1C3w; - + wire signed [15:0] Phase1R0w; + wire signed [15:0] Phase1R1w; + wire signed [15:0] Phase1C0w; + wire signed [15:0] Phase1C1w; + wire signed [15:0] Phase1C2w; + wire signed [15:0] Phase1C3w; +/* always @(*) begin case(Phase1Page) 3'd0:begin @@ -401,7 +401,427 @@ end // case: 3'd7 endcase // case(Phase1Page) end // always @ (*) +*/ + function [15:0] Phase1R0wSel; + input [2:0] Phase1Page; + input [2:0] Phase1Count; + input [15:0] Data00In; + input [15:0] Data01In; + input [15:0] Data02In; + input [15:0] Data03In; + input [15:0] Data04In; + input [15:0] Data05In; + input [15:0] Data06In; + input [15:0] Data07In; + input [15:0] Data08In; + input [15:0] Data09In; + input [15:0] Data10In; + input [15:0] Data11In; + input [15:0] Data12In; + input [15:0] Data13In; + input [15:0] Data14In; + input [15:0] Data15In; + input [15:0] Data16In; + input [15:0] Data17In; + input [15:0] Data18In; + input [15:0] Data19In; + input [15:0] Data20In; + input [15:0] Data21In; + input [15:0] Data22In; + input [15:0] Data23In; + input [15:0] Data24In; + input [15:0] Data25In; + input [15:0] Data26In; + input [15:0] Data27In; + input [15:0] Data28In; + input [15:0] Data29In; + input [15:0] Data30In; + input [15:0] Data31In; + input [15:0] Data32In; + input [15:0] Data33In; + input [15:0] Data34In; + input [15:0] Data35In; + input [15:0] Data36In; + input [15:0] Data37In; + input [15:0] Data38In; + input [15:0] Data39In; + input [15:0] Data40In; + input [15:0] Data41In; + input [15:0] Data42In; + input [15:0] Data43In; + input [15:0] Data44In; + input [15:0] Data45In; + input [15:0] Data46In; + input [15:0] Data47In; + input [15:0] Data48In; + input [15:0] Data49In; + input [15:0] Data50In; + input [15:0] Data51In; + input [15:0] Data52In; + input [15:0] Data53In; + input [15:0] Data54In; + input [15:0] Data55In; + input [15:0] Data56In; + input [15:0] Data57In; + input [15:0] Data58In; + input [15:0] Data59In; + input [15:0] Data60In; + input [15:0] Data61In; + input [15:0] Data62In; + input [15:0] Data63In; + begin + case(Phase1Page) + 3'd0:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data00In; + end + 3'd1: begin + Phase1R0wSel = Data02In; + end + 3'd2: begin + Phase1R0wSel = Data01In; + end + 3'd3: begin + Phase1R0wSel = Data05In; + end + endcase // case(Phase1Count) + end // case: 3'd0 + 3'd1:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data08In; + end + 3'd1: begin + Phase1R0wSel = Data10In; + end + 3'd2: begin + Phase1R0wSel = Data09In; + end + 3'd3: begin + Phase1R0wSel = Data13In; + end + endcase // case(Phase1Count) + end // case: 3'd1 + 3'd2:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data16In; + end + 3'd1: begin + Phase1R0wSel = Data18In; + end + 3'd2: begin + Phase1R0wSel = Data17In; + end + 3'd3: begin + Phase1R0wSel = Data21In; + end + endcase // case(Phase1Count) + end // case: 3'd2 + 3'd3:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data24In; + end + 3'd1: begin + Phase1R0wSel = Data26In; + end + 3'd2: begin + Phase1R0wSel = Data25In; + end + 3'd3: begin + Phase1R0wSel = Data29In; + end + endcase // case(Phase1Count) + end // case: 3'd3 + 3'd4:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data32In; + end + 3'd1: begin + Phase1R0wSel = Data34In; + end + 3'd2: begin + Phase1R0wSel = Data33In; + end + 3'd3: begin + Phase1R0wSel = Data37In; + end + endcase // case(Phase1Count) + end // case: 3'd4 + 3'd5:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data40In; + end + 3'd1: begin + Phase1R0wSel = Data42In; + end + 3'd2: begin + Phase1R0wSel = Data41In; + end + 3'd3: begin + Phase1R0wSel = Data45In; + end + endcase // case(Phase1Count) + end // case: 3'd5 + 3'd6:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data48In; + end + 3'd1: begin + Phase1R0wSel = Data50In; + end + 3'd2: begin + Phase1R0wSel = Data49In; + end + 3'd3: begin + Phase1R0wSel = Data53In; + end + endcase // case(Phase1Count) + end // case: 3'd6 + 3'd7:begin + case(Phase1Count) + 3'd0: begin + Phase1R0wSel = Data56In; + end + 3'd1: begin + Phase1R0wSel = Data58In; + end + 3'd2: begin + Phase1R0wSel = Data57In; + end + 3'd3: begin + Phase1R0wSel = Data61In; + end + endcase // case(Phase1Count) + end // case: 3'd7 + endcase // case(Phase1Page) + end + endfunction + function [15:0] Phase1R1wSel; + input [2:0] Phase1Page; + input [2:0] Phase1Count; + input [15:0] Data00In; + input [15:0] Data01In; + input [15:0] Data02In; + input [15:0] Data03In; + input [15:0] Data04In; + input [15:0] Data05In; + input [15:0] Data06In; + input [15:0] Data07In; + input [15:0] Data08In; + input [15:0] Data09In; + input [15:0] Data10In; + input [15:0] Data11In; + input [15:0] Data12In; + input [15:0] Data13In; + input [15:0] Data14In; + input [15:0] Data15In; + input [15:0] Data16In; + input [15:0] Data17In; + input [15:0] Data18In; + input [15:0] Data19In; + input [15:0] Data20In; + input [15:0] Data21In; + input [15:0] Data22In; + input [15:0] Data23In; + input [15:0] Data24In; + input [15:0] Data25In; + input [15:0] Data26In; + input [15:0] Data27In; + input [15:0] Data28In; + input [15:0] Data29In; + input [15:0] Data30In; + input [15:0] Data31In; + input [15:0] Data32In; + input [15:0] Data33In; + input [15:0] Data34In; + input [15:0] Data35In; + input [15:0] Data36In; + input [15:0] Data37In; + input [15:0] Data38In; + input [15:0] Data39In; + input [15:0] Data40In; + input [15:0] Data41In; + input [15:0] Data42In; + input [15:0] Data43In; + input [15:0] Data44In; + input [15:0] Data45In; + input [15:0] Data46In; + input [15:0] Data47In; + input [15:0] Data48In; + input [15:0] Data49In; + input [15:0] Data50In; + input [15:0] Data51In; + input [15:0] Data52In; + input [15:0] Data53In; + input [15:0] Data54In; + input [15:0] Data55In; + input [15:0] Data56In; + input [15:0] Data57In; + input [15:0] Data58In; + input [15:0] Data59In; + input [15:0] Data60In; + input [15:0] Data61In; + input [15:0] Data62In; + input [15:0] Data63In; + begin + case(Phase1Page) + 3'd0:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data04In; + end + 3'd1: begin + Phase1R1wSel = Data06In; + end + 3'd2: begin + Phase1R1wSel = Data07In; + end + 3'd3: begin + Phase1R1wSel = Data03In; + end + endcase // case(Phase1Count) + end // case: 3'd0 + 3'd1:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data12In; + end + 3'd1: begin + Phase1R1wSel = Data14In; + end + 3'd2: begin + Phase1R1wSel = Data15In; + end + 3'd3: begin + Phase1R1wSel = Data11In; + end + endcase // case(Phase1Count) + end // case: 3'd1 + 3'd2:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data20In; + end + 3'd1: begin + Phase1R1wSel = Data22In; + end + 3'd2: begin + Phase1R1wSel = Data23In; + end + 3'd3: begin + Phase1R1wSel = Data19In; + end + endcase // case(Phase1Count) + end // case: 3'd2 + 3'd3:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data28In; + end + 3'd1: begin + Phase1R1wSel = Data30In; + end + 3'd2: begin + Phase1R1wSel = Data31In; + end + 3'd3: begin + Phase1R1wSel = Data27In; + end + endcase // case(Phase1Count) + end // case: 3'd3 + 3'd4:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data36In; + end + 3'd1: begin + Phase1R1wSel = Data38In; + end + 3'd2: begin + Phase1R1wSel = Data39In; + end + 3'd3: begin + Phase1R1wSel = Data35In; + end + endcase // case(Phase1Count) + end // case: 3'd4 + 3'd5:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data44In; + end + 3'd1: begin + Phase1R1wSel = Data46In; + end + 3'd2: begin + Phase1R1wSel = Data47In; + end + 3'd3: begin + Phase1R1wSel = Data43In; + end + endcase // case(Phase1Count) + end // case: 3'd5 + 3'd6:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data52In; + end + 3'd1: begin + Phase1R1wSel = Data54In; + end + 3'd2: begin + Phase1R1wSel = Data55In; + end + 3'd3: begin + Phase1R1wSel = Data51In; + end + endcase // case(Phase1Count) + end // case: 3'd6 + 3'd7:begin + case(Phase1Count) + 3'd0: begin + Phase1R1wSel = Data60In; + end + 3'd1: begin + Phase1R1wSel = Data62In; + end + 3'd2: begin + Phase1R1wSel = Data63In; + end + 3'd3: begin + Phase1R1wSel = Data59In; + end + endcase // case(Phase1Count) + end // case: 3'd7 + endcase // case(Phase1Page) + end + endfunction + assign Phase1R0w = Phase1R0wSel(Phase1Page, Phase1Count, + Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In, + Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In, + Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In, + Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In, + Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In, + Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In, + Data60In, Data61In, Data62In, Data63In + ); + assign Phase1R1w = Phase1R1wSel(Phase1Page, Phase1Count, + Data00In, Data01In, Data02In, Data03In, Data04In, Data05In, Data06In, Data07In, Data08In, Data09In, + Data10In, Data11In, Data12In, Data13In, Data14In, Data15In, Data16In, Data17In, Data18In, Data19In, + Data20In, Data21In, Data22In, Data23In, Data24In, Data25In, Data26In, Data27In, Data28In, Data29In, + Data30In, Data31In, Data32In, Data33In, Data34In, Data35In, Data36In, Data37In, Data38In, Data39In, + Data40In, Data41In, Data42In, Data43In, Data44In, Data45In, Data46In, Data47In, Data48In, Data49In, + Data50In, Data51In, Data52In, Data53In, Data54In, Data55In, Data56In, Data57In, Data58In, Data59In, + Data60In, Data61In, Data62In, Data63In + ); +/* always @(*) begin case(Phase1Count) 3'd0: begin @@ -432,6 +852,92 @@ endcase // case(Phase1Count) end // always @ (*) +*/ + + function [15:0] Phase1C0wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C0wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C0wSel = 16'd3784; // C2_16 + end + 3'd2: begin + Phase1C0wSel = 16'd4017; // C1_16 + end + 3'd3: begin + Phase1C0wSel = 16'd2276; // C5_16 + end + endcase // case(Phase1Count) + end + endfunction + + function [15:0] Phase1C1wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C1wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C1wSel = 16'd1567; // C6_16 + end + 3'd2: begin + Phase1C1wSel = 16'd799; // C7_16 + end + 3'd3: begin + Phase1C1wSel = 16'd3406; // C3_16 + end + endcase // case(Phase1Count) + end + endfunction + + function [15:0] Phase1C2wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C2wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C2wSel = 16'd1567; // C6_16 + end + 3'd2: begin + Phase1C2wSel = 16'd799; // C7_16 + end + 3'd3: begin + Phase1C2wSel = 16'd3406; // C3_16 + end + endcase // case(Phase1Count) + end + endfunction + + function [15:0] Phase1C3wSel; + input [2:0] Phase1Count; + begin + case(Phase1Count) + 3'd0: begin + Phase1C3wSel = 16'd2896; // C4_16 + end + 3'd1: begin + Phase1C3wSel = 16'd3784; // C2_16 + end + 3'd2: begin + Phase1C3wSel = 16'd4017; // C1_16 + end + 3'd3: begin + Phase1C3wSel = 16'd2276; // C5_16 + end + endcase // case(Phase1Count) + end + endfunction + + assign Phase1C0w = Phase1C0wSel(Phase1Count); + assign Phase1C1w = Phase1C1wSel(Phase1Count); + assign Phase1C2w = Phase1C2wSel(Phase1Count); + assign Phase1C3w = Phase1C3wSel(Phase1Count); reg signed [31:0] Phase1R0r; reg signed [31:0] Phase1R1r; @@ -482,13 +988,17 @@ end // else: !if(!rst) end // always @ (posedge clk or negedge rst) - reg signed [31:0] Phase2A0w; - reg signed [31:0] Phase2A1w; - + wire signed [31:0] Phase2A0w; + wire signed [31:0] Phase2A1w; +/* always @(*) begin Phase2A0w <= Phase1R0r + Phase1R1r; Phase2A1w <= Phase1R2r - Phase1R3r; end +*/ + + assign Phase2A0w = Phase1R0r + Phase1R1r; + assign Phase2A1w = Phase1R2r - Phase1R3r; reg signed [31:0] Phase2Reg [0:7]; @@ -568,13 +1078,17 @@ (Phase3Count == 3'd3)?Phase2Reg[6]: 32'd0; - reg signed [31:0] Phase3A0w; - reg signed [31:0] Phase3A1w; - + wire signed [31:0] Phase3A0w; + wire signed [31:0] Phase3A1w; +/* always @(*) begin Phase3A0w <= Phase3R0w + Phase3R1w; Phase3A1w <= Phase3R0w - Phase3R1w; end +*/ + + assign Phase3A0w = Phase3R0w + Phase3R1w; + assign Phase3A1w = Phase3R0w - Phase3R1w; reg signed [31:0] Phase3Reg [0:7]; 1.2 djpeg/src/jpeg_regdata.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_regdata.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_regdata.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_regdata.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_regdata.v 5 Oct 2006 04:45:15 -0000 1.1 +++ jpeg_regdata.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -7,8 +7,8 @@ // Author : H.Ishihara // E-Mail : hidemi@s... // HomePage : http://www.sweetcafe.jp/ -// Date : 2006/10/01 -// Rev. : 1.1 +// Date : 2007/04/11 +// Rev. : 1.03 //--------------------------------------------------------------------------- // Rev. Date Description //--------------------------------------------------------------------------- @@ -16,18 +16,18 @@ // 1.02 2006/10/04 Remove a RegEnd register. // When reset, clear on OutEnable,PreEnable,DataOut registers. // Remove some comments. +// 1.03 2007/04/11 Don't OutEnable, ImageEnable == 1 and DataOut == 0xFFD9XXXX +// Stop ReadEnable with DataEnd(after 0xFFD9 of ImageData) //--------------------------------------------------------------------------- // $Id: //--------------------------------------------------------------------------- `timescale 1ps / 1ps -module jpeg_regdata - ( +module jpeg_regdata( rst, clk, // Read Data - DataInStart, DataIn, // DataInEnable, // Data Enable DataInRead, // Data Read @@ -35,10 +35,10 @@ // DataOut DataOut, // Data Out DataOutEnable, // Data Out Enable - DataOutEnd, // Data Out End // ImageEnable, + ProcessIdle, // UseData UseBit, // Used data bit @@ -50,16 +50,15 @@ input rst; input clk; - input DataInStart; input [31:0] DataIn; input DataInEnable; output DataInRead; output [31:0] DataOut; output DataOutEnable; - output DataOutEnd; input ImageEnable; + input ProcessIdle; input UseBit; input [6:0] UseWidth; @@ -70,6 +69,8 @@ reg [95:0] RegData; reg [7:0] RegWidth; + reg DataEnd; + assign RegValid = RegWidth > 64; assign DataInRead = RegValid == 1'b0 & DataInEnable == 1'b1; @@ -78,10 +79,7 @@ RegData <= 96'd0; RegWidth <= 8'h00; end else begin - if(DataInStart == 1'b1) begin - RegData <= 96'd0; - RegWidth <= 8'h00; - end else if(RegValid == 1'b0 & DataInEnable == 1'b1) begin + if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin if(ImageEnable == 1'b1) begin if(RegData[39: 8] == 32'hFF00FF00) begin RegWidth <= RegWidth + 16; @@ -117,27 +115,33 @@ RegData[95:64] <= RegData[63:32]; RegData[63:32] <= RegData[31:0]; end - end else begin // if (ImageEnable == 1'b1) + end else begin RegWidth <= RegWidth + 32; RegData[95:64] <= RegData[63:32]; RegData[63:32] <= RegData[31:0]; - end // else: !if(ImageEnable == 1'b1) + end RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]}; - end else if(UseBit == 1'b1) begin // if (RegValid == 1'b0 & DataInEnable == 1'b1) + end else if(UseBit == 1'b1) begin RegWidth <= RegWidth - UseWidth; end else if(UseByte == 1'b1) begin RegWidth <= RegWidth - 8; end else if(UseWord == 1'b1) begin RegWidth <= RegWidth - 16; end - end // else: !if(!rst) - end // always @ (posedge clk or negedge rst) + end + end - assign DataOutEnd = (//RegData[39:24] == 16'hFFD9 | - RegData[31:16] == 16'hFFD9 | - RegData[23: 8] == 16'hFFD9 | - RegData[15: 0] == 16'hFFD9 - ); + always @(posedge clk or negedge rst) begin + if(!rst) begin + DataEnd <= 1'b0; + end else begin + if(ProcessIdle) begin + DataEnd <= 1'b0; + end else if(ImageEnable == 1'b1 & (RegData[39:24] == 16'hFFD9 | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin + DataEnd <= 1'b1; + end + end + end function [31:0] SliceData; input [95:0] RegData; @@ -177,8 +181,8 @@ 8'd95: SliceData = RegData[94:63]; 8'd96: SliceData = RegData[95:64]; default: SliceData = 32'h00000000; - endcase // case(RegWidth) - endfunction // SliceData + endcase + endfunction reg OutEnable; reg PreEnable; @@ -199,7 +203,7 @@ assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0; -endmodule // jpeg_regdata +endmodule \ No newline at end of file 1.2 djpeg/src/jpeg_ycbcr_mem.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_ycbcr_mem.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_ycbcr_mem.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_ycbcr_mem.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_ycbcr_mem.v 5 Oct 2006 04:45:15 -0000 1.1 +++ jpeg_ycbcr_mem.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -50,56 +50,56 @@ output [8:0] DataOutCb; output [8:0] DataOutCr; - reg [8:0] MemYA [0:255]; - reg [8:0] MemYB [0:255]; - reg [8:0] MemCbA [0:63]; - reg [8:0] MemCbB [0:63]; - reg [8:0] MemCrA [0:63]; - reg [8:0] MemCrB [0:63]; + reg [8:0] MemYA [0:127]; + reg [8:0] MemYB [0:127]; + reg [8:0] MemCbA [0:31]; + reg [8:0] MemCbB [0:31]; + reg [8:0] MemCrA [0:31]; + reg [8:0] MemCrB [0:31]; - reg [7:0] WriteAddressA; - reg [7:0] WriteAddressB; + reg [6:0] WriteAddressA; + reg [6:0] WriteAddressB; always @(DataInColor or DataInPage or DataInCount) begin - WriteAddressA[7] <= DataInColor[1]; - WriteAddressB[7] <= DataInColor[1]; + WriteAddressA[6] <= DataInColor[1]; + WriteAddressB[6] <= DataInColor[1]; if(DataInColor[2] == 1'b0) begin if(DataInColor[0] == 1'b0) begin case(DataInCount) 2'h0: begin - WriteAddressA[6:0] <= DataInPage + 0; - WriteAddressB[6:0] <= DataInPage +112; + WriteAddressA[5:0] <= DataInPage + 0; + WriteAddressB[5:0] <= DataInPage +112 -64; end 2'h1: begin - WriteAddressA[6:0] <= DataInPage + 16; - WriteAddressB[6:0] <= DataInPage + 96; + WriteAddressA[5:0] <= DataInPage + 16; + WriteAddressB[5:0] <= DataInPage + 96 -64; end 2'h2: begin - WriteAddressA[6:0] <= DataInPage + 32; - WriteAddressB[6:0] <= DataInPage + 80; + WriteAddressA[5:0] <= DataInPage + 32; + WriteAddressB[5:0] <= DataInPage + 80 -64; end 2'h3: begin - WriteAddressA[6:0] <= DataInPage + 48; - WriteAddressB[6:0] <= DataInPage + 64; + WriteAddressA[5:0] <= DataInPage + 48; + WriteAddressB[5:0] <= DataInPage + 64 -64; end endcase // case(DataInCount) end else begin // if (DataInColor[0] == 1'b0) case(DataInCount) 2'h0: begin - WriteAddressA[6:0] <= DataInPage + 0 +8; - WriteAddressB[6:0] <= DataInPage +112 +8; + WriteAddressA[5:0] <= DataInPage + 0 +8; + WriteAddressB[5:0] <= DataInPage +112 +8 -64; end 2'h1: begin - WriteAddressA[6:0] <= DataInPage + 16 +8; - WriteAddressB[6:0] <= DataInPage + 96 +8; + WriteAddressA[5:0] <= DataInPage + 16 +8; + WriteAddressB[5:0] <= DataInPage + 96 +8 -64; end 2'h2: begin - WriteAddressA[6:0] <= DataInPage + 32 +8; - WriteAddressB[6:0] <= DataInPage + 80 +8; + WriteAddressA[5:0] <= DataInPage + 32 +8; + WriteAddressB[5:0] <= DataInPage + 80 +8 -64; end 2'h3: begin - WriteAddressA[6:0] <= DataInPage + 48 +8; - WriteAddressB[6:0] <= DataInPage + 64 +8; + WriteAddressA[5:0] <= DataInPage + 48 +8; + WriteAddressB[5:0] <= DataInPage + 64 +8 -64; end endcase // case(DataInCount) end // else: !if(DataInColor[0] == 1'b0) @@ -107,19 +107,19 @@ case(DataInCount) 2'h0: begin WriteAddressA[5:0] <= DataInPage + 0; - WriteAddressB[5:0] <= DataInPage + 56; + WriteAddressB[5:0] <= DataInPage + 56 -32; end 2'h1: begin WriteAddressA[5:0] <= DataInPage + 8; - WriteAddressB[5:0] <= DataInPage + 48; + WriteAddressB[5:0] <= DataInPage + 48 -32; end 2'h2: begin WriteAddressA[5:0] <= DataInPage + 16; - WriteAddressB[5:0] <= DataInPage + 40; + WriteAddressB[5:0] <= DataInPage + 40 -32; end 2'h3: begin WriteAddressA[5:0] <= DataInPage + 24; - WriteAddressB[5:0] <= DataInPage + 32; + WriteAddressB[5:0] <= DataInPage + 32 -32; end endcase // case(DataInCount) end // else: !if(DataInColor[2] == 1'b0) @@ -134,15 +134,15 @@ always @(posedge clk) begin if(DataInColor == 3'b100 & DataInEnable == 1'b1) begin - MemCbA[WriteAddressA[5:0]] <= Data0In; - MemCbB[WriteAddressB[5:0]] <= Data1In; + MemCbA[WriteAddressA[4:0]] <= Data0In; + MemCbB[WriteAddressB[4:0]] <= Data1In; end end always @(posedge clk) begin if(DataInColor == 3'b101 & DataInEnable == 1'b1) begin - MemCrA[WriteAddressA[5:0]] <= Data0In; - MemCrB[WriteAddressB[5:0]] <= Data1In; + MemCrA[WriteAddressA[4:0]] <= Data0In; + MemCrB[WriteAddressB[4:0]] <= Data1In; end end @@ -158,14 +158,14 @@ always @(posedge clk) begin RegAdrs <= DataOutAddress; - ReadYA <= MemYA[DataOutAddress]; - ReadYB <= MemYB[DataOutAddress]; + ReadYA <= MemYA[{DataOutAddress[7],DataOutAddress[5:0]}]; + ReadYB <= MemYB[{DataOutAddress[7],DataOutAddress[5:0]}]; - ReadCbA <= MemCbA[{DataOutAddress[7:5],DataOutAddress[3:1]}]; - ReadCrA <= MemCrA[{DataOutAddress[7:5],DataOutAddress[3:1]}]; + ReadCbA <= MemCbA[{DataOutAddress[6:5],DataOutAddress[3:1]}]; + ReadCrA <= MemCrA[{DataOutAddress[6:5],DataOutAddress[3:1]}]; - ReadCbB <= MemCbB[{DataOutAddress[7:5],DataOutAddress[3:1]}]; - ReadCrB <= MemCrB[{DataOutAddress[7:5],DataOutAddress[3:1]}]; + ReadCbB <= MemCbB[{DataOutAddress[6:5],DataOutAddress[3:1]}]; + ReadCrB <= MemCrB[{DataOutAddress[6:5],DataOutAddress[3:1]}]; end // always @ (posedge clk) assign DataOutY = (RegAdrs[6] ==1'b0)?ReadYA:ReadYB; 1.2 djpeg/src/jpeg_ziguzagu_reg.v http://www.opencores.org/cvsweb.shtml/djpeg/src/jpeg_ziguzagu_reg.v.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jpeg_ziguzagu_reg.v =================================================================== RCS file: /cvsroot/hidemi/djpeg/src/jpeg_ziguzagu_reg.v,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jpeg_ziguzagu_reg.v 5 Oct 2006 04:45:16 -0000 1.1 +++ jpeg_ziguzagu_reg.v 16 Apr 2007 20:00:18 -0000 1.2 @@ -169,6 +169,7 @@ integer i; +/* always @(posedge clk or negedge rst) begin if(!rst) begin RegData[0] <= 16'h0000; @@ -246,6 +247,209 @@ end end // else: !if(!rst) end // always @ (posedge clk or negedge rst) +*/ + always @(posedge clk or negedge rst) begin + if(!rst) begin + RegData[0] <= 16'h0000; + RegData[1] <= 16'h0000; + RegData[2] <= 16'h0000; + RegData[3] <= 16'h0000; + RegData[4] <= 16'h0000; + RegData[5] <= 16'h0000; + RegData[6] <= 16'h0000; + RegData[7] <= 16'h0000; + RegData[8] <= 16'h0000; + RegData[9] <= 16'h0000; + RegData[10] <= 16'h0000; + RegData[11] <= 16'h0000; + RegData[12] <= 16'h0000; + RegData[13] <= 16'h0000; + RegData[14] <= 16'h0000; + RegData[15] <= 16'h0000; + RegData[16] <= 16'h0000; + RegData[17] <= 16'h0000; + RegData[18] <= 16'h0000; + RegData[19] <= 16'h0000; + RegData[20] <= 16'h0000; + RegData[21] <= 16'h0000; + RegData[22] <= 16'h0000; + RegData[23] <= 16'h0000; + RegData[24] <= 16'h0000; + RegData[25] <= 16'h0000; + RegData[26] <= 16'h0000; + RegData[27] <= 16'h0000; + RegData[28] <= 16'h0000; + RegData[29] <= 16'h0000; + RegData[30] <= 16'h0000; + RegData[31] <= 16'h0000; + RegData[32] <= 16'h0000; + RegData[33] <= 16'h0000; + RegData[34] <= 16'h0000; + RegData[35] <= 16'h0000; + RegData[36] <= 16'h0000; + RegData[37] <= 16'h0000; + RegData[38] <= 16'h0000; + RegData[39] <= 16'h0000; + RegData[40] <= 16'h0000; + RegData[41] <= 16'h0000; + RegData[42] <= 16'h0000; + RegData[43] <= 16'h0000; + RegData[44] <= 16'h0000; + RegData[45] <= 16'h0000; + RegData[46] <= 16'h0000; + RegData[47] <= 16'h0000; + RegData[48] <= 16'h0000; + RegData[49] <= 16'h0000; + RegData[50] <= 16'h0000; + RegData[51] <= 16'h0000; + RegData[52] <= 16'h0000; + RegData[53] <= 16'h0000; + RegData[54] <= 16'h0000; + RegData[55] <= 16'h0000; + RegData[56] <= 16'h0000; + RegData[57] <= 16'h0000; + RegData[58] <= 16'h0000; + RegData[59] <= 16'h0000; + RegData[60] <= 16'h0000; + RegData[61] <= 16'h0000; + RegData[62] <= 16'h0000; + RegData[63] <= 16'h0000; + end else begin + if(DataInEnable == 1'b1) begin + case(DataInAddress) + 6'd0: begin + RegData[0] <= DataIn; + RegData[1] <= 16'h0000; + RegData[2] <= 16'h0000; + RegData[3] <= 16'h0000; + RegData[4] <= 16'h0000; + RegData[5] <= 16'h0000; + RegData[6] <= 16'h0000; + RegData[7] <= 16'h0000; + RegData[8] <= 16'h0000; + RegData[9] <= 16'h0000; + RegData[10] <= 16'h0000; + RegData[11] <= 16'h0000; + RegData[12] <= 16'h0000; + RegData[13] <= 16'h0000; + RegData[14] <= 16'h0000; + RegData[15] <= 16'h0000; + RegData[16] <= 16'h0000; + RegData[17] <= 16'h0000; + RegData[18] <= 16'h0000; + RegData[19] <= 16'h0000; + RegData[20] <= 16'h0000; + RegData[21] <= 16'h0000; + RegData[22] <= 16'h0000; + RegData[23] <= 16'h0000; + RegData[24] <= 16'h0000; + RegData[25] <= 16'h0000; + RegData[26] <= 16'h0000; + RegData[27] <= 16'h0000; + RegData[28] <= 16'h0000; + RegData[29] <= 16'h0000; + RegData[30] <= 16'h0000; + RegData[31] <= 16'h0000; + RegData[32] <= 16'h0000; + RegData[33] <= 16'h0000; + RegData[34] <= 16'h0000; + RegData[35] <= 16'h0000; + RegData[36] <= 16'h0000; + RegData[37] <= 16'h0000; + RegData[38] <= 16'h0000; + RegData[39] <= 16'h0000; + RegData[40] <= 16'h0000; + RegData[41] <= 16'h0000; + RegData[42] <= 16'h0000; + RegData[43] <= 16'h0000; + RegData[44] <= 16'h0000; + RegData[45] <= 16'h0000; + RegData[46] <= 16'h0000; + RegData[47] <= 16'h0000; + RegData[48] <= 16'h0000; + RegData[49] <= 16'h0000; + RegData[50] <= 16'h0000; + RegData[51] <= 16'h0000; + RegData[52] <= 16'h0000; + RegData[53] <= 16'h0000; + RegData[54] <= 16'h0000; + RegData[55] <= 16'h0000; + RegData[56] <= 16'h0000; + RegData[57] <= 16'h0000; + RegData[58] <= 16'h0000; + RegData[59] <= 16'h0000; + RegData[60] <= 16'h0000; + RegData[61] <= 16'h0000; + RegData[62] <= 16'h0000; + RegData[63] <= 16'h0000; + end + 6'd1: RegData[1] <= DataIn; + 6'd2: RegData[2] <= DataIn; + 6'd3: RegData[3] <= DataIn; + 6'd4: RegData[4] <= DataIn; + 6'd5: RegData[5] <= DataIn; + 6'd6: RegData[6] <= DataIn; + 6'd7: RegData[7] <= DataIn; + 6'd8: RegData[8] <= DataIn; + 6'd9: RegData[9] <= DataIn; + 6'd10: RegData[10] <= DataIn; + 6'd11: RegData[11] <= DataIn; + 6'd12: RegData[12] <= DataIn; + 6'd13: RegData[13] <= DataIn; + 6'd14: RegData[14] <= DataIn; + 6'd15: RegData[15] <= DataIn; + 6'd16: RegData[16] <= DataIn; + 6'd17: RegData[17] <= DataIn; + 6'd18: RegData[18] <= DataIn; + 6'd19: RegData[19] <= DataIn; + 6'd20: RegData[20] <= DataIn; + 6'd21: RegData[21] <= DataIn; + 6'd22: RegData[22] <= DataIn; + 6'd23: RegData[23] <= DataIn; + 6'd24: RegData[24] <= DataIn; + 6'd25: RegData[25] <= DataIn; + 6'd26: RegData[26] <= DataIn; + 6'd27: RegData[27] <= DataIn; + 6'd28: RegData[28] <= DataIn; + 6'd29: RegData[29] <= DataIn; + 6'd30: RegData[30] <= DataIn; + 6'd31: RegData[31] <= DataIn; + 6'd32: RegData[32] <= DataIn; + 6'd33: RegData[33] <= DataIn; + 6'd34: RegData[34] <= DataIn; + 6'd35: RegData[35] <= DataIn; + 6'd36: RegData[36] <= DataIn; + 6'd37: RegData[37] <= DataIn; + 6'd38: RegData[38] <= DataIn; + 6'd39: RegData[39] <= DataIn; + 6'd40: RegData[40] <= DataIn; + 6'd41: RegData[41] <= DataIn; + 6'd42: RegData[42] <= DataIn; + 6'd43: RegData[43] <= DataIn; + 6'd44: RegData[44] <= DataIn; + 6'd45: RegData[45] <= DataIn; + 6'd46: RegData[46] <= DataIn; + 6'd47: RegData[47] <= DataIn; + 6'd48: RegData[48] <= DataIn; + 6'd49: RegData[49] <= DataIn; + 6'd50: RegData[50] <= DataIn; + 6'd51: RegData[51] <= DataIn; + 6'd52: RegData[52] <= DataIn; + 6'd53: RegData[53] <= DataIn; + 6'd54: RegData[54] <= DataIn; + 6'd55: RegData[55] <= DataIn; + 6'd56: RegData[56] <= DataIn; + 6'd57: RegData[57] <= DataIn; + 6'd58: RegData[58] <= DataIn; + 6'd59: RegData[59] <= DataIn; + 6'd60: RegData[60] <= DataIn; + 6'd61: RegData[61] <= DataIn; + 6'd62: RegData[62] <= DataIn; + 6'd63: RegData[63] <= DataIn; + endcase + end + end // else: !if(!rst) + end // always @ (posedge clk or negedge rst) assign Data00Reg = RegData[00]; assign Data01Reg = RegData[01];

     
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