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Message
From: cvs at opencores.org<cvs@o...>
Date: Sat Apr 14 20:38:12 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...
Date: 00/07/04 14:20:38 Modified: jop/modelsim sim.bat sim.do wave.do
Log:
Hardware implementation of iaload and iastore
Revision Changes Path
1.10 jop/modelsim/sim.bat
http://www.opencores.org/cvsweb.shtml/jop/modelsim/sim.bat.diff?r1=1.9&r2=1.10
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sim.bat
===================================================================
RCS file: /cvsroot/martin/jop/modelsim/sim.bat,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- sim.bat 25 Mar 2007 00:18:43 -0000 1.9
+++ sim.bat 14 Apr 2007 18:38:12 -0000 1.10
@@ -9,17 +9,17 @@
vlib grlib
vlib gaisler
vlib techmap
-vcom -work grlib ../ext/gaisler/version.vhd
-vcom -work grlib ../ext/gaisler/stdlib.vhd
-vcom -work grlib ../ext/gaisler/amba.vhd
-vcom -work gaisler ../ext/gaisler/devices.vhd
-vcom -work techmap ../ext/gaisler/gencomp.vhd
-vcom -work gaisler ../ext/gaisler/memctrl.vhd
-vcom -work gaisler ../ext/gaisler/srctrl.vhd
+rem vcom -work grlib ../ext/gaisler/version.vhd
+rem vcom -work grlib ../ext/gaisler/stdlib.vhd
+rem vcom -work grlib ../ext/gaisler/amba.vhd
+rem vcom -work gaisler ../ext/gaisler/devices.vhd
+rem vcom -work techmap ../ext/gaisler/gencomp.vhd
+rem vcom -work gaisler ../ext/gaisler/memctrl.vhd
+rem vcom -work gaisler ../ext/gaisler/srctrl.vhd
vcom %options% %jopdir%/simulation/sim_jop_config_100.vhd
vcom %options% %jopdir%/core/jop_types.vhd
vcom %options% %jopdir%/simpcon/sc_pack.vhd
-vcom %options% %jopdir%/simpcon/sc2ahbsl.vhd
+rem vcom %options% %jopdir%/simpcon/sc2ahbsl.vhd
vcom %options% %jopdir%/simulation/sim_ram.vhd
vcom %options% %jopdir%/simulation/sim_pll.vhd
vcom %options% %jopdir%/simulation/sim_jbc.vhd
@@ -45,8 +45,8 @@
vcom %options% %jopdir%/scio/sc_cnt.vhd
vcom %options% %jopdir%/scio/scio_min.vhd
vcom %options% %jopdir%/core/jopcpu.vhd
-rem vcom %options% %jopdir%/top/jopcyc.vhd
-vcom %options% %jopdir%/top/jop_amba.vhd
+vcom %options% %jopdir%/top/jopcyc.vhd
+rem vcom %options% %jopdir%/top/jop_amba.vhd
vcom %options% %jopdir%/simulation/tb_jop.vhd
rem vcom %options% %jopdir%/top/jop_256x16.vhd
rem vcom %options% %jopdir%/simulation/tb_jop_sram16.vhd
1.6 jop/modelsim/sim.do
http://www.opencores.org/cvsweb.shtml/jop/modelsim/sim.do.diff?r1=1.5&r2=1.6
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sim.do
===================================================================
RCS file: /cvsroot/martin/jop/modelsim/sim.do,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -b -r1.5 -r1.6
--- sim.do 15 Jun 2006 13:27:06 -0000 1.5
+++ sim.do 14 Apr 2007 18:38:12 -0000 1.6
@@ -2,4 +2,5 @@
#view *
view wave
do wave.do
-run 12us
+#run 12us
+run 700ns
1.12 jop/modelsim/wave.do
http://www.opencores.org/cvsweb.shtml/jop/modelsim/wave.do.diff?r1=1.11&r2=1.12
(In the diff below, changes in quantity of whitespace are not shown.)
Index: wave.do
===================================================================
RCS file: /cvsroot/martin/jop/modelsim/wave.do,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -b -r1.11 -r1.12
--- wave.do 25 Mar 2007 00:18:36 -0000 1.11
+++ wave.do 14 Apr 2007 18:38:12 -0000 1.12
@@ -11,6 +11,7 @@
add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_core/cmp_fch/ir
add wave -noupdate -format Logic -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_core/cmp_fch/bsy
add wave -noupdate -format Logic -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_core/cmp_fch/nxt
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_core/cmp_stk/sp
add wave -noupdate -divider io
add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cmp_io/sel_reg
add wave -noupdate -divider {io cnt}
@@ -22,25 +23,24 @@
add wave -noupdate -format Logic -radix hexadecimal /tb_jop/cmp_jop/cmp_io/cmp_cnt/wr
add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cmp_io/cmp_cnt/clock_cnt
add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cmp_io/cmp_cnt/irq_cnt
+add wave -noupdate -divider mem_sc
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/mem_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/mem_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/next_state
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/state
+add wave -noupdate -format Logic -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/bcl_arr_bsy
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/addr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/index
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/addr_calc
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/value
+add wave -noupdate -format Logic /tb_jop/cmp_jop/cpm_cpu/cmp_mem/was_a_store
+add wave -noupdate -format Logic -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/iastore_nxt
+add wave -noupdate -format Logic -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/null_pointer
+add wave -noupdate -format Logic -radix hexadecimal /tb_jop/cmp_jop/cpm_cpu/cmp_mem/bounds_error
+add wave -noupdate -format Literal -radix hexadecimal /tb_jop/main_mem/data
add wave -noupdate -divider SimpCon
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_jop/cmp_jop/cpm_cpu/sc_mem_out
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_jop/cmp_jop/cpm_cpu/sc_mem_in
-add wave -noupdate -divider mem_sc
-add wave -noupdate -format Literal -radix hexadecimal /tb_jop/main_mem/data
-add wave -noupdate -divider sc_mem_if
-add wave -noupdate -divider {bc load}
-add wave -noupdate -divider cache
-add wave -noupdate -divider amba
-add wave -noupdate -format Literal /tb_jop/cmp_jop/cmp_s2a/state
-add wave -noupdate -format Literal /tb_jop/cmp_jop/cmp_s2a/next_state
-add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cmp_s2a/reg_wr_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_jop/cmp_jop/cmp_s2a/reg_rd_data
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_jop/cmp_jop/cmp_s2a/ahbsi
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_jop/cmp_jop/cmp_s2a/ahbso
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_jop/cmp_jop/cmp_s2a/scmi
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_jop/cmp_jop/cmp_s2a/scmo
-add wave -noupdate -divider ahb-memctrl
-add wave -noupdate -format Literal -radix hexadecimal -expand /tb_jop/cmp_jop/srctrl0/r
add wave -noupdate -divider {external signals}
add wave -noupdate -format Literal -radix hexadecimal /tb_jop/main_mem/addr
add wave -noupdate -format Literal -radix hexadecimal /tb_jop/main_mem/data
@@ -54,10 +54,6 @@
add wave -noupdate -format Logic /tb_jop/cmp_jop/fl_noe
add wave -noupdate -format Logic /tb_jop/cmp_jop/fl_nwe
add wave -noupdate -format Logic /tb_jop/cmp_jop/fl_rdy
-add wave -noupdate -divider {wishbone IO}
-add wave -noupdate -divider {wb slave}
-add wave -noupdate -divider exception
-add wave -noupdate -divider execute
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {226600 ps} 0} {{Cursor 2} {693090000 ps} 0} {{Cursor 3} {3450000 ps} 0} {{Cursor 4} {3339704 ps} 0}
configure wave -namecolwidth 228
@@ -73,4 +69,4 @@
configure wave -griddelta 40
configure wave -timeline 0
update
-WaveRestoreZoom {148539 ps} {287265 ps}
+WaveRestoreZoom {0 ps} {201973 ps}
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