OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Sat Apr 14 20:38:10 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...

Date: 00/07/04 14:20:38

Modified: jop/vhdl/core extension.vhd jop_types.vhd jopcpu.vhd Log: Hardware implementation of iaload and iastore Revision Changes Path 1.11 jop/vhdl/core/extension.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/extension.vhd.diff?r1=1.10&r2=1.11 (In the diff below, changes in quantity of whitespace are not shown.) Index: extension.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/core/extension.vhd,v retrieving revision 1.10 retrieving revision 1.11 diff -u -b -r1.10 -r1.11 --- extension.vhd 13 Apr 2007 17:17:21 -0000 1.10 +++ extension.vhd 14 Apr 2007 18:38:09 -0000 1.11 @@ -94,7 +94,7 @@ signal wraddr_msb : std_logic; signal was_a_mem_rd : std_logic; - signal was_a_aload : std_logic; -- select memory for array load + signal was_a_iaload : std_logic; -- select memory for array load signal wr_dly : std_logic; -- generate a bsy with delayed wr @@ -148,7 +148,7 @@ elsif rising_edge(clk) then if (ext_addr=LDMRD) then - if was_a_mem_rd='1' or was_a_aload='1' then + if was_a_mem_rd='1' or was_a_iaload='1' then exr <= mem_out.dout; else exr <= sc_io_in.rd_data; @@ -174,9 +174,11 @@ mem_scio_wr <= '0'; wraddr_wr <= '0'; mem_in.bc_rd <= '0'; + mem_in.iaload <= '0'; + mem_in.iastore <= '0'; mul_wr <= '0'; wr_dly <= '0'; - was_a_aload <= '0'; + was_a_iaload <= '0'; elsif rising_edge(clk) then @@ -184,6 +186,8 @@ mem_scio_wr <= '0'; wraddr_wr <= '0'; mem_in.bc_rd <= '0'; + mem_in.iaload <= '0'; + mem_in.iastore <= '0'; mul_wr <= '0'; wr_dly <= wr; @@ -193,7 +197,7 @@ -- the data to be written (e.g. read address for the memory interface) -- if wr='1' then - was_a_aload <= '0'; + was_a_iaload <= '0'; if ext_addr=STMRA then mem_scio_rd <= '1'; -- start memory or io read @@ -202,7 +206,10 @@ elsif ext_addr=STMWD then mem_scio_wr <= '1'; -- start memory or io write elsif ext_addr=STALD then - was_a_aload <= '0'; + mem_in.iaload <= '1'; -- start an array load + was_a_iaload <= '0'; + elsif ext_addr=STAST then + mem_in.iastore <= '1'; -- start an array store elsif ext_addr=STMUL then mul_wr <= '1'; -- start multiplier -- elsif ext_addr=STBCR then 1.4 jop/vhdl/core/jop_types.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/jop_types.vhd.diff?r1=1.3&r2=1.4 (In the diff below, changes in quantity of whitespace are not shown.) Index: jop_types.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/core/jop_types.vhd,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- jop_types.vhd 13 Apr 2007 17:17:21 -0000 1.3 +++ jop_types.vhd 14 Apr 2007 18:38:09 -0000 1.4 @@ -39,6 +39,8 @@ wr : std_logic; addr_wr : std_logic; bc_rd : std_logic; + iaload : std_logic; + iastore : std_logic; end record; type mem_out_type is record @@ -48,9 +50,15 @@ end record; type exception_type is record - spov : std_logic; + spov : std_logic; -- stack overflow + np : std_logic; -- null pointer + ab : std_logic; -- array out of bounds end record; + constant EXC_SPOV : std_logic_vector(2 downto 0) := "001"; + constant EXC_NP : std_logic_vector(2 downto 0) := "010"; + constant EXC_AB : std_logic_vector(2 downto 0) := "011"; + type irq_in_type is record irq : std_logic; -- interrupt request (positiv edge sensitive) irq_ena : std_logic; -- interrupt enable (pendig int is fired on ena) 1.3 jop/vhdl/core/jopcpu.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/jopcpu.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: jopcpu.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/core/jopcpu.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- jopcpu.vhd 13 Apr 2007 17:17:21 -0000 1.2 +++ jopcpu.vhd 14 Apr 2007 18:38:09 -0000 1.3 @@ -124,7 +124,11 @@ port map ( clk => clk, reset => reset, - din => stack_tos, + ain => stack_tos, + bin => stack_nos, + + np_exc => exc_req.np, + ab_exc => exc_req.ab, mem_in => mem_in, mem_out => mem_out,