OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Fri Apr 13 19:17:22 CEST 2007
Subject: [cvs-checkins] MODIFIED: jop ...

Date: 00/07/04 13:19:17

Modified: jop/vhdl/core extension.vhd jop_types.vhd jopcpu.vhd Log: Constants for ext_addr encoding, records for extension/mem interface Revision Changes Path 1.10 jop/vhdl/core/extension.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/extension.vhd.diff?r1=1.9&r2=1.10 (In the diff below, changes in quantity of whitespace are not shown.) Index: extension.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/core/extension.vhd,v retrieving revision 1.9 retrieving revision 1.10 diff -u -b -r1.9 -r1.10 --- extension.vhd 18 Mar 2007 01:46:46 -0000 1.9 +++ extension.vhd 13 Apr 2007 17:17:21 -0000 1.10 @@ -6,34 +6,22 @@ -- -- resources on Cyclone -- --- xxx LCs, xx MHz +-- 55 LCs (+xxx for mul) -- -- ext_addr and wr are one cycle earlier than data -- dout is read one cycle after rd -- --- address mapping: --- --- 0 free (former IO address) --- 1 free (former IO data read/write) --- 2 st mem_rd_addr start read --- 2 ld mem_rd_data read data --- 3 st wraddr store write address --- 4 st mem_wr_data start write --- 5 ld mul result --- 5 st mul operand a, b and start mul --- 6 free --- 7 st start bytecode load (or cache) --- 7 ld read new pc base (for cache version) --- --- todo: +-- address mapping see jop_tpyes.vhd -- -- -- 2004-09-11 first version -- 2005-04-05 Reserve negative addresses for wishbone interface --- 2005-04-07 generate bsy from delayed wr or'ed with mem_bsy +-- 2005-04-07 generate bsy from delayed wr or'ed with mem_out.bsy -- 2005-05-30 added wishbone interface -- 2005-11-28 Substitute WB interface by the SimpCon IO interface ;-) -- All IO devices are now memory mapped +-- 2007-04-13 Changed memory connection to records +-- New array instructions -- @@ -61,14 +49,8 @@ dout : out std_logic_vector(31 downto 0); -- to stack -- mem interface - - mem_rd : out std_logic; - mem_wr : out std_logic; - mem_addr_wr : out std_logic; - mem_bc_rd : out std_logic; - mem_data : in std_logic_vector(31 downto 0); -- output of memory module - mem_bcstart : in std_logic_vector(31 downto 0); -- start of method in bc cache - mem_bsy : in std_logic; + mem_in : out mem_in_type; + mem_out : in mem_out_type; -- SimpCon master io interface @@ -108,10 +90,12 @@ signal mem_scio_wr : std_logic; -- memory or SimpCon IO write signal wraddr_wr : std_logic; - -- msb selects mem/wishbone + -- msb selects mem/io signal wraddr_msb : std_logic; signal was_a_mem_rd : std_logic; + signal was_a_aload : std_logic; -- select memory for array load + signal wr_dly : std_logic; -- generate a bsy with delayed wr signal exr, exr_next : std_logic_vector(31 downto 0); -- extension data register @@ -145,7 +129,7 @@ -- is allowed. But we are not using interleaved mul/mem/io -- operations in jvm.asm anyway. -- --- TAKE CARE when mem_bcstart is read! +-- TAKE CARE when mem_out.bcstart is read! -- -- ** bcstart is also read without a mem_bc_rd JOP wr !!! *** -- => a combinatorial mux select on rd and ext_adr==7! @@ -163,17 +147,17 @@ exr <= (others => '0'); elsif rising_edge(clk) then - if (ext_addr="010") then - if was_a_mem_rd='1' then - exr <= mem_data; + if (ext_addr=LDMRD) then + if was_a_mem_rd='1' or was_a_aload='1' then + exr <= mem_out.dout; else exr <= sc_io_in.rd_data; end if; - elsif (ext_addr="101") then + elsif (ext_addr=LDMUL) then exr <= mul_dout; - -- elsif (ext_addr="111") then + -- elsif (ext_addr=LDBCSTART) then else - exr <= mem_bcstart; + exr <= mem_out.bcstart; end if; end if; @@ -189,16 +173,17 @@ mem_scio_rd <= '0'; mem_scio_wr <= '0'; wraddr_wr <= '0'; - mem_bc_rd <= '0'; + mem_in.bc_rd <= '0'; mul_wr <= '0'; wr_dly <= '0'; + was_a_aload <= '0'; elsif rising_edge(clk) then mem_scio_rd <= '0'; mem_scio_wr <= '0'; wraddr_wr <= '0'; - mem_bc_rd <= '0'; + mem_in.bc_rd <= '0'; mul_wr <= '0'; wr_dly <= wr; @@ -208,20 +193,21 @@ -- the data to be written (e.g. read address for the memory interface) -- if wr='1' then - -- if ext_addr="000" then - -- io_addr_wr <= '1'; -- store real io address - -- elsif ext_addr="010" then - if ext_addr="010" then - mem_scio_rd <= '1'; -- start memory or wishbone read - elsif ext_addr="011" then + was_a_aload <= '0'; + + if ext_addr=STMRA then + mem_scio_rd <= '1'; -- start memory or io read + elsif ext_addr=STMWA then wraddr_wr <= '1'; -- store write address - elsif ext_addr="100" then - mem_scio_wr <= '1'; -- start memory or wishbone write - elsif ext_addr="101" then + elsif ext_addr=STMWD then + mem_scio_wr <= '1'; -- start memory or io write + elsif ext_addr=STALD then + was_a_aload <= '0'; + elsif ext_addr=STMUL then mul_wr <= '1'; -- start multiplier - -- elsif ext_addr="111" then + -- elsif ext_addr=STBCR then else - mem_bc_rd <= '1'; -- start bc read + mem_in.bc_rd <= '1'; -- start bc read end if; end if; @@ -231,14 +217,14 @@ -- -- memory read/write only from positive addresses -- - mem_rd <= mem_scio_rd and not ain(31); - mem_wr <= mem_scio_wr and not wraddr_msb; - mem_addr_wr <= wraddr_wr; + mem_in.rd <= mem_scio_rd and not ain(31); + mem_in.wr <= mem_scio_wr and not wraddr_msb; + mem_in.addr_wr <= wraddr_wr; -- a JOP wr generates the first bsy cycle -- the following are generated by the memory -- system or the SimpCon device - bsy <= wr_dly or mem_bsy or sc_bsy; + bsy <= wr_dly or mem_out.bsy or sc_bsy; sc_bsy <= '1' when sc_io_in.rdy_cnt=3 else '0'; 1.3 jop/vhdl/core/jop_types.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/jop_types.vhd.diff?r1=1.2&r2=1.3 (In the diff below, changes in quantity of whitespace are not shown.) Index: jop_types.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/core/jop_types.vhd,v retrieving revision 1.2 retrieving revision 1.3 diff -u -b -r1.2 -r1.3 --- jop_types.vhd 18 Mar 2007 01:46:46 -0000 1.2 +++ jop_types.vhd 13 Apr 2007 17:17:21 -0000 1.3 @@ -9,21 +9,42 @@ package jop_types is - -- not usefull as it's inout - type io_port_type is record - l : std_logic_vector(20 downto 1); - r : std_logic_vector(20 downto 1); - t : std_logic_vector(6 downto 1); - b : std_logic_vector(10 downto 1); - end record; +-- +-- extension address constants (used in extension.vhd and Instrucion.java) +-- +-- 0 st mem_rd_addr start read +-- 0 ld mem_rd_data read data +-- 1 st wraddr store write address +-- 2 st mem_wr_data start write +-- 5 st mul operand a, b and start mul +-- 5 ld mul result +-- 6 free +-- 7 st start bytecode load (or cache) +-- 7 ld read new pc base (for cache version) +-- + constant STMRA : std_logic_vector(2 downto 0) := "000"; + constant STMWA : std_logic_vector(2 downto 0) := "001"; + constant STMWD : std_logic_vector(2 downto 0) := "010"; + constant STALD : std_logic_vector(2 downto 0) := "011"; + constant STAST : std_logic_vector(2 downto 0) := "100"; + constant STMUL : std_logic_vector(2 downto 0) := "101"; + constant STBCR : std_logic_vector(2 downto 0) := "111"; - type ser_in_type is record - rxd : std_logic; - ncts : std_logic; + constant LDMRD : std_logic_vector(2 downto 0) := "000"; + constant LDMUL : std_logic_vector(2 downto 0) := "101"; + constant LDBCSTART : std_logic_vector(2 downto 0) := "111"; + + type mem_in_type is record + rd : std_logic; + wr : std_logic; + addr_wr : std_logic; + bc_rd : std_logic; end record; - type ser_out_type is record - txd : std_logic; - nrts : std_logic; + + type mem_out_type is record + dout : std_logic_vector(31 downto 0); + bcstart : std_logic_vector(31 downto 0); -- start of method in bc cache + bsy : std_logic; end record; type exception_type is record @@ -37,4 +58,21 @@ exc_int : std_logic; -- exception interrupt end record; + type ser_in_type is record + rxd : std_logic; + ncts : std_logic; + end record; + type ser_out_type is record + txd : std_logic; + nrts : std_logic; + end record; + + -- not usefull as it's inout + type io_port_type is record + l : std_logic_vector(20 downto 1); + r : std_logic_vector(20 downto 1); + t : std_logic_vector(6 downto 1); + b : std_logic_vector(10 downto 1); + end record; + end jop_types; 1.2 jop/vhdl/core/jopcpu.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/core/jopcpu.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: jopcpu.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/core/jopcpu.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- jopcpu.vhd 19 Mar 2007 11:33:59 -0000 1.1 +++ jopcpu.vhd 13 Apr 2007 17:17:21 -0000 1.2 @@ -4,6 +4,7 @@ -- The JOP CPU -- -- 2007-03-16 creation +-- 2007-04-13 Changed memory connection to records -- -- todo: clean up: substitute all signals by records @@ -63,28 +64,14 @@ -- extension/mem interface - signal mem_rd : std_logic; - signal mem_wr : std_logic; - signal mem_addr_wr : std_logic; - signal mem_bc_rd : std_logic; - signal mem_dout : std_logic_vector(31 downto 0); - signal mem_bcstart : std_logic_vector(31 downto 0); - signal mem_bsy : std_logic; + signal mem_in : mem_in_type; + signal mem_out : mem_out_type; + signal bsy : std_logic; signal jbc_addr : std_logic_vector(jpc_width-1 downto 0); signal jbc_data : std_logic_vector(7 downto 0); --- memory interface - - signal ram_addr : std_logic_vector(17 downto 0); - signal ram_dout : std_logic_vector(31 downto 0); - signal ram_din : std_logic_vector(31 downto 0); - signal ram_dout_en : std_logic; - signal ram_ncs : std_logic; - signal ram_noe : std_logic; - signal ram_nwe : std_logic; - -- SimpCon io interface signal sp_ov : std_logic; @@ -122,13 +109,8 @@ bsy => bsy, dout => stack_din, - mem_rd => mem_rd, - mem_wr => mem_wr, - mem_addr_wr => mem_addr_wr, - mem_bc_rd => mem_bc_rd, - mem_data => mem_dout, - mem_bcstart => mem_bcstart, - mem_bsy => mem_bsy, + mem_in => mem_in, + mem_out => mem_out, sc_io_out => sc_io_out, sc_io_in => sc_io_in @@ -137,31 +119,21 @@ cmp_mem: entity work.mem_sc generic map ( jpc_width => jpc_width, - block_bits => block_bits, - addr_bits => 21 + block_bits => block_bits ) port map ( clk => clk, reset => reset, din => stack_tos, - mem_rd => mem_rd, - mem_wr => mem_wr, - mem_addr_wr => mem_addr_wr, - mem_bc_rd => mem_bc_rd, - dout => mem_dout, - bcstart => mem_bcstart, - bsy => mem_bsy, + mem_in => mem_in, + mem_out => mem_out, jbc_addr => jbc_addr, jbc_data => jbc_data, - address => sc_mem_out.address, - wr_data => sc_mem_out.wr_data, - rd => sc_mem_out.rd, - wr => sc_mem_out.wr, - rd_data => sc_mem_in.rd_data, - rdy_cnt => sc_mem_in.rdy_cnt + sc_mem_out => sc_mem_out, + sc_mem_in => sc_mem_in ); end rtl;