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From: cvs at opencores.org<cvs@o...>
Date: Thu Apr 12 22:21:33 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/04 12:22:21

Modified: aemb/rtl/verilog aeMB_regfile.v
Log:
Moved testbench into /sim/verilog.

Simulation cleanups.


Revision Changes Path
1.8 aemb/rtl/verilog/aeMB_regfile.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.7&r2=1.8

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -b -r1.7 -r1.8
--- aeMB_regfile.v 11 Apr 2007 16:30:06 -0000 1.7
+++ aeMB_regfile.v 12 Apr 2007 20:21:33 -0000 1.8
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.7 2007/04/11 16:30:06 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.8 2007/04/12 20:21:33 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
@@ -25,6 +25,10 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.8 2007/04/12 20:21:33 sybreon
+ * Moved testbench into /sim/verilog.
+ * Simulation cleanups.
+ *
* Revision 1.7 2007/04/11 16:30:06 sybreon
* Cosmetic changes
*
@@ -417,10 +421,6 @@
end
end

- always @(negedge nclk) begin
- if ((fWE & (rRD_== 5'd0)) || (fLNK & (rRD_== 5'd0)) || (fLD & (rRD_== 5'd0))) $displayh("!!! Warning: Write to R0 !!!");
- end
-
endmodule // aeMB_regfile