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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Tue Mar 27 02:33:09 CEST 2007
    Subject: [cvs-checkins] MODIFIED: s1_core ...
    Top
    Date: 00/07/03 27:02:33

    Modified: s1_core/tools/src gtkwave.sav
    Log:
    Removed list of formerly dirty signals, to improve waveforms readability.




    Revision Changes Path
    1.2 s1_core/tools/src/gtkwave.sav

    http://www.opencores.org/cvsweb.shtml/s1_core/tools/src/gtkwave.sav.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: gtkwave.sav
    ===================================================================
    RCS file: /cvsroot/fafa1971/s1_core/tools/src/gtkwave.sav,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- gtkwave.sav 4 Jan 2007 02:22:22 -0000 1.1
    +++ gtkwave.sav 27 Mar 2007 00:33:08 -0000 1.2
    @@ -1,4 +1,4 @@
    -*-15.938658 7196010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
    +*-21,125721 7674010 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
    @28
    testbench.sys_reset
    testbench.sys_clock
    @@ -30,89 +30,3 @@
    testbench.wb_ack
    @22
    testbench.wb_datain[63:0]
    - at 28
    -testbench.s1_top_0.sparc_0.exu.ecl.lsu_exu_flush_pipe_w
    -testbench.s1_top_0.sparc_0.exu.ecl.mdqctl.div_kill
    -testbench.s1_top_0.sparc_0.exu.ecl.mdqctl.flush_w1
    -testbench.s1_top_0.sparc_0.exu.ecl.mdqctl.mul_kill
    -testbench.s1_top_0.sparc_0.exu.ecl.writeback.ecl_exu_kill_m
    -testbench.s1_top_0.sparc_0.exu.ecl.writeback.flush_w1
    -testbench.s1_top_0.sparc_0.exu.ecl.writeback.kill_ld_g2
    -testbench.s1_top_0.sparc_0.exu.lsu_exu_flush_pipe_w
    -testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_dff.din[0]
    -testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_dff.q[0]
    -testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_dff.so[0]
    -testbench.s1_top_0.sparc_0.ffu.ctl.blk_asi_m
    -testbench.s1_top_0.sparc_0.ffu.ctl.dff_flush_w2.din[0]
    -testbench.s1_top_0.sparc_0.ffu.ctl.dff_flush_w2.q[0]
    -testbench.s1_top_0.sparc_0.ffu.ctl.dff_flush_w2.so[0]
    -testbench.s1_top_0.sparc_0.ffu.ctl.dff_killed_w.din[0]
    -testbench.s1_top_0.sparc_0.ffu.ctl.flush_w
    -testbench.s1_top_0.sparc_0.ffu.ctl.flush_w2
    -testbench.s1_top_0.sparc_0.ffu.ctl.ieee_trap
    -testbench.s1_top_0.sparc_0.ffu.ctl.kill_fp
    -testbench.s1_top_0.sparc_0.ffu.ctl.kill_m
    -testbench.s1_top_0.sparc_0.ffu.ctl.lsu_ffu_blk_asi_e
    -testbench.s1_top_0.sparc_0.ffu.ctl.lsu_ffu_flush_pipe_w
    -testbench.s1_top_0.sparc_0.ffu.ctl.visctl.flush_w2
    -testbench.s1_top_0.sparc_0.ffu.lsu_ffu_blk_asi_e
    -testbench.s1_top_0.sparc_0.ffu.lsu_ffu_flush_pipe_w
    -testbench.s1_top_0.sparc_0.ifu.dcl.all_flush_w
    -testbench.s1_top_0.sparc_0.ifu.dcl.all_flush_w2
    -testbench.s1_top_0.sparc_0.ifu.dcl.flshw2_ff.so[0]
    -testbench.s1_top_0.sparc_0.ifu.dcl.tlu_ifu_flush_pipe_w
    -testbench.s1_top_0.sparc_0.ifu.dec.dtu_fcl_flush_sonly_e
    -testbench.s1_top_0.sparc_0.ifu.dtu_fcl_flush_sonly_e
    -testbench.s1_top_0.sparc_0.ifu.fcl.canthr_sd
    -testbench.s1_top_0.sparc_0.ifu.fcl.canthr_sm
    -testbench.s1_top_0.sparc_0.ifu.fcl.canthr_sw
    -testbench.s1_top_0.sparc_0.ifu.fcl.dtu_fcl_flush_sonly_e
    -testbench.s1_top_0.sparc_0.ifu.fcl.ely_kill_thread_m
    -testbench.s1_top_0.sparc_0.ifu.fcl.ely_kill_thread_s2
    -testbench.s1_top_0.sparc_0.ifu.fcl.fcl_fdp_noswpc_sel_old_l_bf
    -testbench.s1_top_0.sparc_0.ifu.fcl.fcl_fdp_noswpc_sel_tnpc_l_bf
    -testbench.s1_top_0.sparc_0.ifu.fcl.fcl_fdp_pcoor_f
    -testbench.s1_top_0.sparc_0.ifu.fcl.flshm_ff.din[0]
    -testbench.s1_top_0.sparc_0.ifu.fcl.flshm_ff.q[0]
    -testbench.s1_top_0.sparc_0.ifu.fcl.flshm_ff.so[0]
    -testbench.s1_top_0.sparc_0.ifu.fcl.flush_pipe_w
    -testbench.s1_top_0.sparc_0.ifu.fcl.flush_pipe_w2
    -testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_all_m
    -testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_m
    -testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_qual_e
    -testbench.s1_top_0.sparc_0.ifu.fcl.flush_sonly_qual_m
    -testbench.s1_top_0.sparc_0.ifu.fcl.fp_ff.din[0]
    -testbench.s1_top_0.sparc_0.ifu.fcl.fp_ff.q[0]
    -testbench.s1_top_0.sparc_0.ifu.fcl.fp_ff.so[0]
    -testbench.s1_top_0.sparc_0.ifu.fcl.fdp_fcl_va2_bf
    -testbench.s1_top_0.sparc_0.ifu.fcl.itlb_access_gnt
    -testbench.s1_top_0.sparc_0.ifu.fcl.itlbrstf_ff.din[0]
    -testbench.s1_top_0.sparc_0.ifu.fcl.kill_thread_d
    -testbench.s1_top_0.sparc_0.ifu.fcl.kill_thread_m
    -testbench.s1_top_0.sparc_0.ifu.fcl.kill_thread_s2
    -testbench.s1_top_0.sparc_0.ifu.fcl.kill_curr_m
    -testbench.s1_top_0.sparc_0.ifu.fcl.ntpc_thisthr
    -testbench.s1_top_0.sparc_0.ifu.fcl.rst_itlb_stv_l
    -testbench.s1_top_0.sparc_0.ifu.fcl.starv_ctr.rst_ctr_l
    -testbench.s1_top_0.sparc_0.ifu.fcl.tlu_ifu_trapnpc_vld_w1
    -testbench.s1_top_0.sparc_0.ifu.fcl.tlu_ifu_trappc_vld_w1
    -testbench.s1_top_0.sparc_0.ifu.fcl.tlu_ifu_flush_pipe_w
    -testbench.s1_top_0.sparc_0.ifu.fcl.va2_f
    -testbench.s1_top_0.sparc_0.ifu.fcl.va2_ff.din[0] -testbench.s1_top_0.sparc_0.ifu.fcl.va2_ff.q[0] -testbench.s1_top_0.sparc_0.ifu.fcl.va2_ff.so[0] -testbench.s1_top_0.sparc_0.ifu.fcl_fdp_noswpc_sel_old_l_bf -testbench.s1_top_0.sparc_0.ifu.fcl_fdp_noswpc_sel_tnpc_l_bf -testbench.s1_top_0.sparc_0.ifu.fcl_fdp_pcoor_f -testbench.s1_top_0.sparc_0.ifu.fdp.fcl_fdp_noswpc_sel_tnpc_l_bf -testbench.s1_top_0.sparc_0.ifu.fdp.fcl_fdp_pcoor_f -testbench.s1_top_0.sparc_0.ifu.fdp.t0_pcbf_mux.sel0_l -testbench.s1_top_0.sparc_0.ifu.fdp.t0_pcbf_mux.sel2_l -testbench.s1_top_0.sparc_0.ifu.fdp.t0tnpc_mux.sel3_l -testbench.s1_top_0.sparc_0.ifu.fdp.t0tnpc_mux.sel2_l -testbench.s1_top_0.sparc_0.ifu.ifqctl.cans_ff.din[0] -testbench.s1_top_0.sparc_0.ifu.ifqctl.canthr_d1 -testbench.s1_top_0.sparc_0.ifu.ifqctl.canthr_s1 -testbench.s1_top_0.sparc_0.ifu.ifqctl.mil0.cancel_mil -testbench.s1_top_0.sparc_0.ifu.ifqctl.mil0.cancel_next -testbench.s1_top_0.sparc_0.ifu.ifqctl.mil0.fsm_ifc_mil_cancel

     
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