OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Tue Mar 27 01:11:06 CEST 2007
Subject: [cvs-checkins] MODIFIED: s1_core ...

Date: 00/07/03 27:01:11

Modified: s1_core/hdl filelist.dc filelist.fpga filelist.icarus filelist.vcs Log: Updated filelists according to the new OpenSPARC 1.4, and add some minor changes like Stephen Williams's suggestion to use $(S1_ROOT) in the filelists for Icarus Verilog (he's the author!). Revision Changes Path 1.2 s1_core/hdl/filelist.dc http://www.opencores.org/cvsweb.shtml/s1_core/hdl/filelist.dc.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: filelist.dc =================================================================== RCS file: /cvsroot/fafa1971/s1_core/hdl/filelist.dc,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- filelist.dc 4 Jan 2007 02:13:18 -0000 1.1 +++ filelist.dc 26 Mar 2007 23:11:05 -0000 1.2 @@ -1,213 +1,214 @@ -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/u1_lib.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/m1_lib.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclccr.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_reg.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_rndrob.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_shft.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_dp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_part_add32.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ffu_vis.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_cmp35.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ctr5.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dcl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_dec.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_errdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fcl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_fdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_imd.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_incr46.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_invctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_lru4.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_mbist.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_milfsm.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par16.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par32.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_par34.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_rndrob.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_sscan.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_swpla.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_ifu_wseldp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_asi_decode.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dc_parity_gen.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcache_lfsr.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dcdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_dctldp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_excpctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_pcx_qmon.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl1.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qctl2.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp1.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_qdp2.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_rrobin_picker2.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_ctldp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_stb_rwdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tagdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/lsu_tlbdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_cntl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_dp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_mul_top.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_buf.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cpx_spc_rpt.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spc_pcx_buf.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_ctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_lsurpt1.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaddr.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maaeqb.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mactl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_madp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_maexp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mald.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mamul.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mared.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_mast.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/spu_wen.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_dec64.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_intdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_penc64.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_addern_32.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_hyperv.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_incr64.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_misctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_ctl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_mmu_dp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_pib.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_prencoder16.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_rrobin_picker.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tcl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/tlu_tdp.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/rst_ctrl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/int_ctrl.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/spc2wbm.v -analyze -format verilog -define { FPGA_SYN } /usr/design/simplyrisc-s1/hdl/rtl/s1_top/s1_top.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/macrocell/sparc_libs/m1_lib.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/macrocell/sparc_libs/u1_lib.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_cm16x40b.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_cm16x40.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_dcm.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_efa.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_rf_16x65.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_rf_16x81.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_frf.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_icd.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_idct.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_irf.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_l2d_32k.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_l2d.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x128d.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x108.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_scm.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cclk_sync.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gl_hz.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xa0.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xa1.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xb0.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xb1.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xb2.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xb3.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc0.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc1.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc2.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc3.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc4.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc5.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc6.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/flop_rptrs_xc7.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_rng.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header_ctu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header_dup.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cluster_header_sync.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/dbl_buf.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_clib.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sync_pulse_synchronizer.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_bist.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/synchronizer_asr_dup.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/test_stub_scan.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/ucb_bus_in.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/ucb_bus_out.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/ucb_flow_2buf.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/ucb_flow_jbi.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/ucb_flow_spi.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/ucb_noflow.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/mul64.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spc_pcx_buf.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_ctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_lsurpt1.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaddr.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maaeqb.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mactl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_madp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_maexp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mald.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mamul.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mared.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_mast.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/spu_wen.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_incr64.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_misctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_pib.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tcl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/sparc_core/tlu_tdp.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/rst_ctrl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/int_ctrl.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/spc2wbm.v +analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } ~/s1_core/hdl/rtl/s1_top/s1_top.v /* If you modify this file remember to run update_filelist so that filelist.dc gets updated!!! */ 1.2 s1_core/hdl/filelist.fpga http://www.opencores.org/cvsweb.shtml/s1_core/hdl/filelist.fpga.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: filelist.fpga =================================================================== RCS file: /cvsroot/fafa1971/s1_core/hdl/filelist.fpga,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- filelist.fpga 4 Jan 2007 02:13:18 -0000 1.1 +++ filelist.fpga 26 Mar 2007 23:11:05 -0000 1.2 @@ -1,213 +1,216 @@ -/usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/u1_lib.v -/usr/design/simplyrisc-s1/hdl/macrocell/sparc_libs/m1_lib.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v 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+$(S1_ROOT)/hdl/rtl/sparc_core/spu_maexp.v +$(S1_ROOT)/hdl/rtl/sparc_core/spu_mald.v +$(S1_ROOT)/hdl/rtl/sparc_core/spu_mamul.v +$(S1_ROOT)/hdl/rtl/sparc_core/spu_mared.v +$(S1_ROOT)/hdl/rtl/sparc_core/spu_mast.v +$(S1_ROOT)/hdl/rtl/sparc_core/spu_wen.v +$(S1_ROOT)/hdl/rtl/sparc_core/sparc_tlu_dec64.v +$(S1_ROOT)/hdl/rtl/sparc_core/sparc_tlu_intctl.v +$(S1_ROOT)/hdl/rtl/sparc_core/sparc_tlu_intdp.v +$(S1_ROOT)/hdl/rtl/sparc_core/sparc_tlu_penc64.v +$(S1_ROOT)/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_addern_32.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_hyperv.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_incr64.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_misctl.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_mmu_ctl.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_mmu_dp.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_pib.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_prencoder16.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_rrobin_picker.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_tcl.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_tdp.v +$(S1_ROOT)/hdl/rtl/s1_top/rst_ctrl.v +$(S1_ROOT)/hdl/rtl/s1_top/int_ctrl.v +$(S1_ROOT)/hdl/rtl/s1_top/spc2wbm.v +$(S1_ROOT)/hdl/rtl/s1_top/s1_top.v ++incdir+$(S1_ROOT)/hdl/rtl/sparc_core/include ++incdir+$(S1_ROOT)/hdl/rtl/s1_top +define+FPGA_SYN ++define+FPGA_SYN_1THREAD ++define+FPGA_SYN_NO_SPU 1.2 s1_core/hdl/filelist.icarus http://www.opencores.org/cvsweb.shtml/s1_core/hdl/filelist.icarus.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: filelist.icarus =================================================================== RCS file: /cvsroot/fafa1971/s1_core/hdl/filelist.icarus,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- filelist.icarus 4 Jan 2007 02:13:18 -0000 1.1 +++ filelist.icarus 26 Mar 2007 23:11:05 -0000 1.2 @@ -1,214 +1,218 @@ -/usr/design/simplyrisc-s1/hdl/behav/sparc_libs/m1_lib.v -/usr/design/simplyrisc-s1/hdl/behav/sparc_libs/u1_lib.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v -/usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v 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+$(S1_ROOT)/hdl/rtl/sparc_core/tlu_mmu_ctl.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_mmu_dp.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_pib.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_prencoder16.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_rrobin_picker.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_tcl.v +$(S1_ROOT)/hdl/rtl/sparc_core/tlu_tdp.v +$(S1_ROOT)/hdl/rtl/s1_top/rst_ctrl.v +$(S1_ROOT)/hdl/rtl/s1_top/int_ctrl.v +$(S1_ROOT)/hdl/rtl/s1_top/spc2wbm.v +$(S1_ROOT)/hdl/rtl/s1_top/s1_top.v +$(S1_ROOT)/hdl/behav/testbench/mem_harness.v +$(S1_ROOT)/hdl/behav/testbench/testbench.v ++incdir+$(S1_ROOT)/hdl/rtl/sparc_core/include ++incdir+$(S1_ROOT)/hdl/rtl/s1_top ++define+FPGA_SYN ++define+FPGA_SYN_1THREAD ++define+FPGA_SYN_NO_SPU 1.2 s1_core/hdl/filelist.vcs http://www.opencores.org/cvsweb.shtml/s1_core/hdl/filelist.vcs.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: filelist.vcs =================================================================== RCS file: /cvsroot/fafa1971/s1_core/hdl/filelist.vcs,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- filelist.vcs 4 Jan 2007 02:13:18 -0000 1.1 +++ filelist.vcs 26 Mar 2007 23:11:05 -0000 1.2 @@ -1,214 +1,215 @@ --v /usr/design/simplyrisc-s1/hdl/behav/sparc_libs/m1_lib.v --v /usr/design/simplyrisc-s1/hdl/behav/sparc_libs/u1_lib.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_cm16x40b.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcd.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_dcm.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_efa.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_frf.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_icd.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_idct.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_irf.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_32k.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_bot.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_l2d_rep_top.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x128d.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x160.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf16x32.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x108.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x152b.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_rf32x80.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_scm.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_r_tlb.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x65.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rf_16x81.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_48x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_hdr_64x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_128x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_48x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_64x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_inv_96x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_scanlasr_2x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_cclk_sync.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_center_3inv.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_192x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_224x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_288x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_192x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_224x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_inv_r90_256x.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gclk_sctag_3inv.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_fdbk.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_hz.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_rstce_rtl.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_clk_gl_vrt_all.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa0.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xa1.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb0.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb1.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb2.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xb3.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc0.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc1.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc2.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc3.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc4.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc5.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc6.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/flop_rptrs_xc7.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/bw_rng.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_ctu.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_dup.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cluster_header_sync.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/cmp_sram_redhdr.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/dbl_buf.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_clib.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/swrvr_dlib.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sync_pulse_synchronizer.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_bist.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/synchronizer_asr_dup.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/test_stub_scan.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_in.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_bus_out.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_2buf.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_jbi.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_flow_spi.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/ucb_noflow.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/mul64.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluadder64.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_alulogic.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluor32.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluspr.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_32eql.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_div_yreg.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v --v /usr/design/simplyrisc-s1/hdl/rtl/sparc_core/sparc_exu_ecl.v --v /usr/design/simplyrisc-s1/hdl/