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From: cvs at opencores.org<cvs@o...>
Date: Mon Mar 26 14:21:32 CEST 2007
Subject: [cvs-checkins] MODIFIED: aemb ...
Date: 00/07/03 26:14:21

Modified: aemb/rtl/verilog aeMB_regfile.v
Log:
Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.




Revision Changes Path
1.2 aemb/rtl/verilog/aeMB_regfile.v

http://www.opencores.org/cvsweb.shtml/aemb/rtl/verilog/aeMB_regfile.v.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: aeMB_regfile.v
===================================================================
RCS file: /cvsroot/sybreon/aemb/rtl/verilog/aeMB_regfile.v,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- aeMB_regfile.v 9 Mar 2007 17:52:17 -0000 1.1
+++ aeMB_regfile.v 26 Mar 2007 12:21:31 -0000 1.2
@@ -9,7 +9,7 @@
// Status : Unknown, Use with caution!

/*
- * $Id: aeMB_regfile.v,v 1.1 2007/03/09 17:52:17 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.2 2007/03/26 12:21:31 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
@@ -34,6 +34,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.2 2007/03/26 12:21:31 sybreon
+ * Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.
+ *
* Revision 1.1 2007/03/09 17:52:17 sybreon
* initial import
*
@@ -71,7 +74,7 @@
reg [31:0] r18,r19,r1A,r1B,r1C,r1D,r1E,r1F;

// FLAGS
- wire fWE = rRWE;
+ wire fWE = rRWE & ~rDWBWE;
wire fLNK = rLNK;
wire fLD = rDWBSTB ^ rDWBWE;

@@ -134,13 +137,13 @@
5'h1D: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1D;
5'h1E: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1E;
5'h1F: rDWBDAT <= #1 (fDFWD) ? rRESULT : r1F;
- endcase // case(rRD)
+ endcase // case (rRD)
end else begin // if (drun)
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rDWBDAT <= 32'h0;
// End of automatics
- end
+ end // else: !if(drun)

// Load Registers
reg [31:0] rREGA, rREGB;
@@ -185,7 +188,7 @@
5'h02: rREGA <= #1 r02;
5'h01: rREGA <= #1 r01;
5'h00: rREGA <= #1 r00;
- endcase // case(rRA)
+ endcase // case (rRA)

case (rRB)
5'h1F: rREGB <= #1 r1F;
@@ -220,14 +223,14 @@
5'h02: rREGB <= #1 r02;
5'h01: rREGB <= #1 r01;
5'h00: rREGB <= #1 r00;
- endcase // case(rRB)
+ endcase // case (rRB)
end else begin // if (drun)
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rREGA <= 32'h0;
rREGB <= 32'h0;
// End of automatics
- end
+ end // else: !if(drun)


// Normal Registers
@@ -366,7 +369,7 @@
r1E <= #1 (fR1E & fLD) ? wDWBDAT : (fR1E & fLNK) ? rPC_ : (fR1E & fWE) ? rRESULT : r1E;
r1F <= #1 (fR1F & fLD) ? wDWBDAT : (fR1F & fLNK) ? rPC_ : (fR1F & fWE) ? rRESULT : r1F;
*/
- end // if (drun)
+ end // else: !if(!nrst)

// Special Registers
always @(negedge nclk or negedge nrst) @@ -386,7 +389,7 @@ // R11 - Exception r11 <= #1 (rFSM == 2'b10) ? rPC : // Needs verification (!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ? rRESULT : r11; - end + end // else: !if(!nrst) endmodule // aeMB_regfile