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Message
From: cvs at opencores.org<cvs@o...>
Date: Sun Mar 25 03:07:53 CEST 2007
Subject: [cvs-checkins] MODIFIED: simpcon ...
Date: 00/07/03 25:03:07 Modified: simpcon/vhdl sc_sram32.vhd sc_uart.vhd scio_min.vhd
Log:
update from JOP
Revision Changes Path
1.5 simpcon/vhdl/sc_sram32.vhd
http://www.opencores.org/cvsweb.shtml/simpcon/vhdl/sc_sram32.vhd.diff?r1=1.4&r2=1.5
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sc_sram32.vhd
===================================================================
RCS file: /cvsroot/martin/simpcon/vhdl/sc_sram32.vhd,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -b -r1.4 -r1.5
--- sc_sram32.vhd 6 Dec 2005 14:35:08 -0000 1.4
+++ sc_sram32.vhd 25 Mar 2007 01:07:53 -0000 1.5
@@ -14,6 +14,7 @@
--
--
-- 2005-11-22 first version
+-- 2007-03-17 changed SimpCon to records
--
Library IEEE;
@@ -21,6 +22,7 @@
use ieee.numeric_std.all;
use work.jop_types.all;
+use work.sc_pack.all;
entity sc_mem_if is
generic (ram_ws : integer; addr_bits : integer);
@@ -29,13 +31,11 @@
clk, reset : in std_logic;
--- SimpCon interface
-
- address : in std_logic_vector(addr_bits-1 downto 0);
- wr_data : in std_logic_vector(31 downto 0);
- rd, wr : in std_logic;
- rd_data : out std_logic_vector(31 downto 0);
- rdy_cnt : out unsigned(1 downto 0);
+--
+-- SimpCon memory interface
+--
+ sc_mem_out : in sc_mem_out_type;
+ sc_mem_in : out sc_in_type;
-- memory interface
@@ -71,9 +71,10 @@
begin
+ assert MEM_ADDR_SIZE>=addr_bits report "Too less address bits";
ram_dout_en <= dout_ena;
- rdy_cnt <= cnt;
+ sc_mem_in.rdy_cnt <= cnt;
--
-- Register memory address, write data and read data
@@ -84,18 +85,18 @@
ram_addr <= (others => '0');
ram_dout <= (others => '0');
- rd_data <= (others => '0');
+ sc_mem_in.rd_data <= (others => '0');
elsif rising_edge(clk) then
- if rd='1' or wr='1' then
- ram_addr <= address;
+ if sc_mem_out.rd='1' or sc_mem_out.wr='1' then
+ ram_addr <= sc_mem_out.address(addr_bits-1 downto 0);
end if;
- if wr='1' then
- ram_dout <= wr_data;
+ if sc_mem_out.wr='1' then
+ ram_dout <= sc_mem_out.wr_data;
end if;
if rd_data_ena='1' then
- rd_data <= ram_din;
+ sc_mem_in.rd_data <= ram_din;
end if;
end if;
@@ -119,7 +120,7 @@
--
-- next state logic
--
-process(state, rd, wr, wait_state)
+process(state, sc_mem_out.rd, sc_mem_out.wr, wait_state)
begin
@@ -129,14 +130,14 @@
case state is
when idl =>
- if rd='1' then
+ if sc_mem_out.rd='1' then
if ram_ws=0 then
-- then we omit state rd1!
next_state <= rd2;
else
next_state <= rd1;
end if;
- elsif wr='1' then
+ elsif sc_mem_out.wr='1' then
next_state <= wr1;
end if;
@@ -151,14 +152,14 @@
next_state <= idl;
-- This should do to give us a pipeline
-- level of 2 for read
- if rd='1' then
+ if sc_mem_out.rd='1' then
if ram_ws=0 then
-- then we omit state rd1!
next_state <= rd2;
else
next_state <= rd1;
end if;
- elsif wr='1' then
+ elsif sc_mem_out.wr='1' then
next_state <= wr1;
end if;
@@ -258,7 +259,7 @@
cnt <= wait_state(1 downto 0)-1;
end if;
- if rd='1' or wr='1' then
+ if sc_mem_out.rd='1' or sc_mem_out.wr='1' then
wait_state <= to_unsigned(ram_ws+1, 4);
if ram_ws<3 then
cnt <= to_unsigned(ram_ws+1, 2);
1.2 simpcon/vhdl/sc_uart.vhd
http://www.opencores.org/cvsweb.shtml/simpcon/vhdl/sc_uart.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: sc_uart.vhd
===================================================================
RCS file: /cvsroot/martin/simpcon/vhdl/sc_uart.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- sc_uart.vhd 6 Dec 2005 14:35:36 -0000 1.1
+++ sc_uart.vhd 25 Mar 2007 01:07:53 -0000 1.2
@@ -31,6 +31,8 @@
-- 2003-09-19 sync ncts in!
-- 2004-03-23 two stop bits
-- 2005-11-30 change interface to SimpCon
+-- 2006-08-07 rxd input register with clk to avoid Quartus tsu violation
+-- 2006-08-13 use 3 FFs for the rxd input at clk
--
@@ -116,7 +118,7 @@
signal rf_full : std_logic;
signal rf_half : std_logic;
- signal rxd_reg : std_logic;
+ signal rxd_reg : std_logic_vector(2 downto 0);
signal rx_buf : std_logic_vector(2 downto 0); -- sync in, filter
signal rx_d : std_logic; -- rx serial data
@@ -180,6 +182,10 @@
elsif rising_edge(clk) then
+ rxd_reg(0) <= rxd; -- to avoid setup timing error in Quartus
+ rxd_reg(1) <= rxd_reg(0);
+ rxd_reg(2) <= rxd_reg(1);
+
if (clk16=clk16_cnt) then -- 16 x serial clock
clk16 := 0;
--
@@ -207,8 +213,7 @@
--
-- sync in filter buffer
--
- rxd_reg <= rxd; -- to avoid setup timing error in Quartus
- rx_buf(0) <= rxd_reg;
+ rx_buf(0) <= rxd_reg(2);
rx_buf(2 downto 1) <= rx_buf(1 downto 0);
else
clk16 := clk16 + 1;
1.2 simpcon/vhdl/scio_min.vhd
http://www.opencores.org/cvsweb.shtml/simpcon/vhdl/scio_min.vhd.diff?r1=1.1&r2=1.2
(In the diff below, changes in quantity of whitespace are not shown.)
Index: scio_min.vhd
===================================================================
RCS file: /cvsroot/martin/simpcon/vhdl/scio_min.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- scio_min.vhd 29 Dec 2005 17:50:36 -0000 1.1
+++ scio_min.vhd 25 Mar 2007 01:07:53 -0000 1.2
@@ -23,6 +23,7 @@
-- 2003-07-09 created
-- 2005-08-27 ignore ncts on uart
-- 2005-11-30 changed to SimpCon
+-- 2007-03-17 use records
--
--
@@ -32,26 +33,26 @@
use ieee.numeric_std.all;
use work.jop_types.all;
+use work.sc_pack.all;
+use work.jop_config.all;
entity scio is
-generic (addr_bits : integer);
port (
clk : in std_logic;
reset : in std_logic;
--- SimpCon interface
-
- address : in std_logic_vector(addr_bits-1 downto 0);
- wr_data : in std_logic_vector(31 downto 0);
- rd, wr : in std_logic;
- rd_data : out std_logic_vector(31 downto 0);
- rdy_cnt : out unsigned(1 downto 0);
-
--- interrupt
+--
+-- SimpCon IO interface
+--
+ sc_io_out : in sc_io_out_type;
+ sc_io_in : out sc_in_type;
- irq : out std_logic;
- irq_ena : out std_logic;
+--
+-- Interrupts from IO devices
+--
+ irq_in : out irq_in_type;
+ exc_req : in exception_type;
-- serial interface
@@ -105,19 +106,19 @@
assert SLAVE_CNT <= 2**DECODE_BITS report "Wrong constant in scio";
- sel <= to_integer(unsigned(address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));
+ sel <= to_integer(unsigned(sc_io_out.address(SLAVE_ADDR_BITS+DECODE_BITS-1 downto SLAVE_ADDR_BITS)));
-- What happens when sel_reg > SLAVE_CNT-1??
- rd_data <= sc_dout(sel_reg);
- rdy_cnt <= sc_rdy_cnt(sel_reg);
+ sc_io_in.rd_data <= sc_dout(sel_reg);
+ sc_io_in.rdy_cnt <= sc_rdy_cnt(sel_reg);
--
-- Connect SLAVE_CNT simple test slaves
--
gsl: for i in 0 to SLAVE_CNT-1 generate
- sc_rd(i) <= rd when i=sel else '0';
- sc_wr(i) <= wr when i=sel else '0';
+ sc_rd(i) <= sc_io_out.rd when i=sel else '0';
+ sc_wr(i) <= sc_io_out.wr when i=sel else '0';
end generate;
@@ -129,7 +130,7 @@
if (reset='1') then
sel_reg <= 0;
elsif rising_edge(clk) then
- if rd='1' then
+ if sc_io_out.rd='1' then
sel_reg <= sel;
end if;
end if;
@@ -143,15 +144,16 @@
clk => clk,
reset => reset,
- address => address(SLAVE_ADDR_BITS-1 downto 0),
- wr_data => wr_data,
+ address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0),
+ wr_data => sc_io_out.wr_data,
rd => sc_rd(0),
wr => sc_wr(0),
rd_data => sc_dout(0),
rdy_cnt => sc_rdy_cnt(0),
- irq => irq,
- irq_ena => irq_ena,
+ irq_in => irq_in,
+ exc_req => exc_req,
+
wd => wd
);
@@ -168,8 +170,8 @@
clk => clk,
reset => reset,
- address => address(SLAVE_ADDR_BITS-1 downto 0),
- wr_data => wr_data,
+ address => sc_io_out.address(SLAVE_ADDR_BITS-1 downto 0),
+ wr_data => sc_io_out.wr_data,
rd => sc_rd(1),
wr => sc_wr(1),
rd_data => sc_dout(1),
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