OPENCORES.ORG

From: cvs at opencores.org<cvs@o...>
Date: Sun Mar 25 01:17:48 CET 2007
Subject: [cvs-checkins] MODIFIED: jop ...

Date: 00/07/03 25:01:17

Modified: jop/vhdl/simpcon sc2ahbsl.vhd Log: one cycle shorter read Revision Changes Path 1.2 jop/vhdl/simpcon/sc2ahbsl.vhd http://www.opencores.org/cvsweb.shtml/jop/vhdl/simpcon/sc2ahbsl.vhd.diff?r1=1.1&r2=1.2 (In the diff below, changes in quantity of whitespace are not shown.) Index: sc2ahbsl.vhd =================================================================== RCS file: /cvsroot/martin/jop/vhdl/simpcon/sc2ahbsl.vhd,v retrieving revision 1.1 retrieving revision 1.2 diff -u -b -r1.1 -r1.2 --- sc2ahbsl.vhd 24 Mar 2007 22:41:50 -0000 1.1 +++ sc2ahbsl.vhd 25 Mar 2007 00:17:48 -0000 1.2 @@ -46,13 +46,9 @@ signal state : state_type; signal next_state : state_type; - signal reg_addr : std_logic_vector(MEM_ADDR_SIZE-1 downto 0); signal reg_wr_data : std_logic_vector(31 downto 0); signal reg_rd_data : std_logic_vector(31 downto 0); - signal reg_rd : std_logic; - signal reg_wr : std_logic; - begin -- @@ -80,26 +76,19 @@ ahbsi.hirq <= (others => '0'); -- interrupt result bus --- depends on state.... - scmi.rd_data <= reg_rd_data; -- --- Register memory address, write data and read data --- do we need all those for amba? +-- Register write data -- process(clk, reset) begin if reset='1' then - reg_addr <= (others => '0'); reg_wr_data <= (others => '0'); elsif rising_edge(clk) then - if scmo.rd='1' or scmo.wr='1' then - reg_addr <= scmo.address; - end if; if scmo.wr='1' then reg_wr_data <= scmo.wr_data; end if; @@ -107,48 +96,9 @@ end if; end process; - ----- ----- The address MUX slightly violates the Avalon ----- specification. The address changes from the sc_address ----- to the registerd address in the second cycle. However, ----- as both registers contain the same value there should be ----- no real glitch. For synchronous peripherals this is not ----- an issue. For asynchronous peripherals (SRAM) the possible ----- glitch should be short enough to be not seen on the output ----- pins. ----- ---process(scmo.rd, scmo.w, sc_address, reg_addr) ---begin --- if sc_rd='1' or sc_wr='1' then --- av_address(addr_bits-1+2 downto 2) <= sc_address; --- else --- av_address(addr_bits-1+2 downto 2) <= reg_addr; --- end if; ---end process; --- ----- Same game for the write data and write/read control ---process(sc_wr, sc_wr_data, reg_wr_data) ---begin --- if sc_wr='1' then --- av_writedata <= sc_wr_data; --- else --- av_writedata <= reg_wr_data; --- end if; ---end process; --- --- av_write <= sc_wr or reg_wr; --- av_read <= sc_rd or reg_rd; --- --- --- -- -- next state logic -- --- At the moment we do not support back to back read --- or write. We don't need it for JOP, right? --- If needed just copy the idl code to rd and wr. --- process(state, scmo, ahbso.hready) begin @@ -171,6 +121,11 @@ when rd => next_state <= idl; + if scmo.rd='1' then + next_state <= rdw; + elsif scmo.wr='1' then + next_state <= wrw; + end if; when wrw => if ahbso.hready='1' then @@ -179,6 +134,11 @@ when wr => next_state <= idl; + if scmo.rd='1' then + next_state <= rdw; + elsif scmo.wr='1' then + next_state <= wrw; + end if; end case; @@ -195,16 +155,38 @@ if (reset='1') then state <= idl; reg_rd_data <= (others => '0'); - scmi.rdy_cnt <= "00"; - reg_rd <= '0'; - reg_wr <= '0'; elsif rising_edge(clk) then state <= next_state; + + case next_state is + + when idl => + + when rdw => + + when rd => + reg_rd_data <= ahbso.hrdata; + + when wrw => + + when wr => + + end case; + + end if; +end process; + +-- +-- combinatorial state machine output +-- +process(next_state) + +begin + scmi.rdy_cnt <= "00"; - reg_rd <= '0'; - reg_wr <= '0'; + scmi.rd_data <= reg_rd_data; case next_state is @@ -212,20 +194,17 @@ when rdw => scmi.rdy_cnt <= "11"; - reg_rd <= '1'; when rd => - reg_rd_data <= ahbso.hrdata; + scmi.rd_data <= ahbso.hrdata; when wrw => scmi.rdy_cnt <= "11"; - reg_wr <= '1'; when wr => end case; - end if; end process; end rtl;