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    Navigation: All forums > Cvs-checkins > Message List > Message Post

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    From: cvs at opencores.org<cvs@o...>
    Date: Mon Feb 26 17:53:51 CET 2007
    Subject: [cvs-checkins] MODIFIED: usb_dongle_fpga ...
    Top
    Date: 00/07/02 26:17:53

    Modified: usb_dongle_fpga/sw/Uspp SerialPort_win.py
    Log:
    one ; in line end possible runtime error


    Revision Changes Path
    1.3 usb_dongle_fpga/sw/Uspp/SerialPort_win.py

    http://www.opencores.org/cvsweb.shtml/usb_dongle_fpga/sw/Uspp/SerialPort_win.py.diff?r1=1.2&r2=1.3

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: SerialPort_win.py
    ===================================================================
    RCS file: /cvsroot/nuubik/usb_dongle_fpga/sw/Uspp/SerialPort_win.py,v
    retrieving revision 1.2
    retrieving revision 1.3
    diff -u -b -r1.2 -r1.3
    --- SerialPort_win.py 22 Feb 2007 19:01:13 -0000 1.2
    +++ SerialPort_win.py 26 Feb 2007 16:53:51 -0000 1.3
    @@ -272,7 +272,7 @@
    WriteFile(self.__handle, pack('2c', buffer[a], buffer[a+1]), overlapped)
    else:
    WriteFile(self.__handle, pack('2c', buffer[a], chr(0xFF)), overlapped)
    - a+=2;
    + a+=2
    else:
    overlapped=OVERLAPPED()
    overlapped.hEvent=CreateEvent(None, 0,0, None)



     
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