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From: cvs at opencores.org<cvs@o...>
Date: Thu Jan 25 23:25:30 CET 2007
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/07/01 25:23:25

Modified: rise/vhdl tb_rise_uart.vhd
Log:
- Added gap between characters sent and changed last character to CR.


Revision Changes Path
1.3 rise/vhdl/tb_rise_uart.vhd

http://www.opencores.org/cvsweb.shtml/rise/vhdl/tb_rise_uart.vhd.diff?r1=1.2&r2=1.3

(In the diff below, changes in quantity of whitespace are not shown.)

Index: tb_rise_uart.vhd
===================================================================
RCS file: /cvsroot/cwalter/rise/vhdl/tb_rise_uart.vhd,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -b -r1.2 -r1.3
--- tb_rise_uart.vhd 25 Jan 2007 22:06:41 -0000 1.2
+++ tb_rise_uart.vhd 25 Jan 2007 22:25:30 -0000 1.3
@@ -88,21 +88,22 @@

wait for 20us;

+ -- send a 'CR' = 0x0A
rx <= '0'; -- 8 startbit
wait for 8600ns;
+ rx <= '0'; -- 8 datenbits
+ wait for 8600ns;
rx <= '1'; -- 8 datenbits
wait for 8600ns;
rx <= '0'; -- 8 datenbits
wait for 8600ns;
- rx <= '0'; -- 8 datenbits
+ rx <= '1'; -- 8 datenbits
wait for 8600ns;
rx <= '0'; -- 8 datenbits
wait for 8600ns;
rx <= '0'; -- 8 datenbits
wait for 8600ns;
- rx <= '1'; -- 8 datenbits
- wait for 8600ns;
- rx <= '1'; -- 8 datenbits
+ rx <= '0'; -- 8 datenbits
wait for 8600ns;
rx <= '0'; -- 8 datenbits
wait for 8600ns;