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From: cvs at opencores.org<cvs@o...>
Date: Thu Jan 25 22:08:25 CET 2007
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/07/01 25:22:08

Modified: rise/tools bin2vhd.c bin2vhd.exe
Log:
- Fixed binary to VHDL converter.


Revision Changes Path
1.2 rise/tools/bin2vhd.c

http://www.opencores.org/cvsweb.shtml/rise/tools/bin2vhd.c.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: bin2vhd.c
===================================================================
RCS file: /cvsroot/cwalter/rise/tools/bin2vhd.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- bin2vhd.c 25 Jan 2007 20:32:30 -0000 1.1
+++ bin2vhd.c 25 Jan 2007 21:08:25 -0000 1.2
@@ -25,7 +25,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * File: $Id: bin2vhd.c,v 1.1 2007/01/25 20:32:30 cwalter Exp $
+ * File: $Id: bin2vhd.c,v 1.2 2007/01/25 21:08:25 cwalter Exp $
*/

#include <stdio.h>
@@ -115,7 +115,7 @@
void
vWriteEntity( FILE * pxOutputFile )
{
- fprintf( pxOutputFile, "libary IEEE;\n" );
+ fprintf( pxOutputFile, "library IEEE;\n" );
fprintf( pxOutputFile, "use IEEE.STD_LOGIC_1164.all;\n" );
fprintf( pxOutputFile, "use IEEE.NUMERIC_STD.all;\n" );
fprintf( pxOutputFile, "entity %s is\n", VHDL_ENTITY_NAME );
@@ -123,7 +123,7 @@
fprintf( pxOutputFile, " clk : in std_logic;\n" );
fprintf( pxOutputFile, " addr : in std_logic_vector(%d downto 0 );\n", ( ADDRESS_BITS - 1 ) );
fprintf( pxOutputFile, " data : out std_logic_vector(%d downto 0 ) );\n", ( DATA_BITS - 1 ) );
- fprintf( pxOutputFile, ")\n" );
+ fprintf( pxOutputFile, "end %s;\n", VHDL_ENTITY_NAME );
fprintf( pxOutputFile, "\n" );
}

@@ -131,24 +131,24 @@
vWriteArchitectureHeader( FILE * pxOutputFile )
{
fprintf( pxOutputFile, "architecture %s of %s is\n", VHDL_ARCHITECTURE_NAME, VHDL_ENTITY_NAME );
- fprintf( pxOutputFile, " signal data_next : std_logic_vector(%d downto 0 ) );\n",
+ fprintf( pxOutputFile, " signal sig_data_next : std_logic_vector(%d downto 0 );\n",
( DATA_BITS - 1 ) );
if( IS_SYNCHRONOUS )
{
- fprintf( pxOutputFile, " signal data_int : std_logic_vector(%d downto 0 ) );\n",
+ fprintf( pxOutputFile, " signal sig_data_int : std_logic_vector(%d downto 0 ) );\n",
( DATA_BITS - 1 ) );
fprintf( pxOutputFile, "begin\n" );
- fprintf( pxOutputFile, " data <= signal_data_int\n" );
+ fprintf( pxOutputFile, " data <= sig_data_int\n" );
fprintf( pxOutputFile, "process (clk)\n" );
fprintf( pxOutputFile, " if clk'event and clk = '1' then\n" );
- fprintf( pxOutputFile, " signal_data_int <= signal_data_next;\n" );
+ fprintf( pxOutputFile, " sig_data_int <= sig_data_next;\n" );
fprintf( pxOutputFile, " end if;\n" );
fprintf( pxOutputFile, "end process;\n" );
}
else
{
fprintf( pxOutputFile, "begin\n" );
- fprintf( pxOutputFile, " data <= signal_data_next\n" );
+ fprintf( pxOutputFile, " data <= sig_data_next;\n" );
}
fprintf( pxOutputFile, "\n" );
fprintf( pxOutputFile, " process( addr )\n" );
@@ -169,7 +169,7 @@
{
sprintf( &arucBuffer[i], "%02X", pucData[iBytePos] );
}
- fprintf( pxOutputFile, " when x\"%s\" => signal_data_next <= x\"%*s\"\n",
+ fprintf( pxOutputFile, " when x\"%s\" => sig_data_next <= x\"%*s\";\n",
pcAddress2Hex( uiProgrammCounter ), DATA_BITS / 4, arucBuffer );
uiProgrammCounter += PC_INCREMENT;
}
@@ -178,11 +178,11 @@
void
vWriteArchitectureFooter( FILE * pxOutputFile )
{
- fprintf( pxOutputFile, " when others => signal_data_next <= ( others => '0' );\n" );
+ fprintf( pxOutputFile, " when others => sig_data_next <= ( others => '0' );\n" );
fprintf( pxOutputFile, " end case;\n" );
fprintf( pxOutputFile, " end process;\n" );
fprintf( pxOutputFile, "\n" );
- fprintf( pxOutputFile, "end %s", VHDL_ARCHITECTURE_NAME );
+ fprintf( pxOutputFile, "end %s;", VHDL_ARCHITECTURE_NAME );
}

const char *
1.2 rise/tools/bin2vhd.exe http://www.opencores.org/cvsweb.shtml/rise/tools/bin2vhd.exe?rev=1.2&content-type=text/x-cvsweb-markup <<Binary file>>