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From: cvs at opencores.org<cvs@o...>
Date: Thu Jan 25 01:25:27 CET 2007
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/07/01 25:01:25

Modified: rise/vhdl dmem.vhd
Log:
uart_address_0 was a latch -> changed


Revision Changes Path
1.10 rise/vhdl/dmem.vhd

http://www.opencores.org/cvsweb.shtml/rise/vhdl/dmem.vhd.diff?r1=1.9&r2=1.10

(In the diff below, changes in quantity of whitespace are not shown.)

Index: dmem.vhd
===================================================================
RCS file: /cvsroot/ustadler/rise/vhdl/dmem.vhd,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -b -r1.9 -r1.10
--- dmem.vhd 24 Jan 2007 22:03:45 -0000 1.9
+++ dmem.vhd 25 Jan 2007 00:25:27 -0000 1.10
@@ -145,6 +145,7 @@
mem_addr <= (others => '0');
mem_data_in <= (others => '0');
mem_wr_enable <= '0';
+ uart_address <= (others => '0');

uart_wr <= '0';
uart_wr_data <= (others => '0');
@@ -157,6 +158,7 @@
-- accessing UART

uart_address <= addr (1 downto 0);
+
if wr_enable = '1' then
uart_wr <= '1';
uart_wr_data <= data_in;