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From: cvs at opencores.org<cvs@o...>
Date: Wed Jan 24 23:21:16 CET 2007
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/07/01 24:23:21

Modified: rise/vhdl if_stage.vhd
Log:
Added test program for testing uart.


Revision Changes Path
1.13 rise/vhdl/if_stage.vhd

http://www.opencores.org/cvsweb.shtml/rise/vhdl/if_stage.vhd.diff?r1=1.12&r2=1.13

(In the diff below, changes in quantity of whitespace are not shown.)

Index: if_stage.vhd
===================================================================
RCS file: /cvsroot/jlechner/rise/vhdl/if_stage.vhd,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -b -r1.12 -r1.13
--- if_stage.vhd 17 Jan 2007 02:00:44 -0000 1.12
+++ if_stage.vhd 24 Jan 2007 22:21:16 -0000 1.13
@@ -186,22 +186,65 @@
-- e: e0 31 st R3,[R1]
-- 10: 70 20 jmp R2

+
+-- process (cur_pc)
+-- begin
+-- case cur_pc is
+-- when x"0000" => if_id_register_next.ir <= x"8100"; -- ld R1,#0x0
+-- when x"0002" => if_id_register_next.ir <= x"9110"; -- ldhb R1,#0x10
+-- when x"0004" => if_id_register_next.ir <= x"e001"; -- st R0,[R1]
+-- when x"0006" => if_id_register_next.ir <= x"820a"; -- ld R2,#0xa
+-- when x"0008" => if_id_register_next.ir <= x"9200"; -- ldhb R2,#0x0
+
+-- when x"000A" => if_id_register_next.ir <= x"a031"; -- ld R3,[R1]
+-- when x"000C" => if_id_register_next.ir <= x"1831"; -- add R3,#0x1
+-- when x"000E" => if_id_register_next.ir <= x"e031"; -- st R3,[R1]
+-- when x"0010" => if_id_register_next.ir <= x"7020"; -- jmp R2
+-- when others => if_id_register_next.ir <= x"0000"; -- nop
+-- end case;
+-- end process;
+
+
+
+-- UART sample
+
process (cur_pc)
begin
case cur_pc is
- when x"0000" => if_id_register_next.ir <= x"8100"; -- ld R1,#0x0
- when x"0002" => if_id_register_next.ir <= x"9110"; -- ldhb R1,#0x10
- when x"0004" => if_id_register_next.ir <= x"e001"; -- st R0,[R1]
- when x"0006" => if_id_register_next.ir <= x"820a"; -- ld R2,#0xa
- when x"0008" => if_id_register_next.ir <= x"9200"; -- ldhb R2,#0x0
-
- when x"000A" => if_id_register_next.ir <= x"a031"; -- ld R3,[R1]
- when x"000C" => if_id_register_next.ir <= x"1831"; -- add R3,#0x1
- when x"000E" => if_id_register_next.ir <= x"e031"; -- st R3,[R1]
- when x"0010" => if_id_register_next.ir <= x"7020"; -- jmp R2
+ when x"0000" => if_id_register_next.ir <= x"8800"; -- ld R8,#0x0
+ when x"0002" => if_id_register_next.ir <= x"9880"; -- ldhb R8,#0x80
+ when x"0004" => if_id_register_next.ir <= x"8901"; -- ld R9,#0x1
+ when x"0006" => if_id_register_next.ir <= x"9980"; -- ldhb R9,#0x80
+ when x"0008" => if_id_register_next.ir <= x"8b10"; -- ld R11,#0x10
+
+ when x"000A" => if_id_register_next.ir <= x"9b00"; -- ldhb R11,#0x0
+ when x"000C" => if_id_register_next.ir <= x"8c1c"; -- ld R12,#0x1c
+ when x"000E" => if_id_register_next.ir <= x"9c00"; -- ldhb R12,#0x0
+ when x"0010" => if_id_register_next.ir <= x"70c0"; -- jmp R12 (test)
+
+ -- when x"0010" => if_id_register_next.ir <= x"a028"; -- ld R2,[R8]
+
+ when x"0012" => if_id_register_next.ir <= x"8302"; -- ld R3,#0x2
+ when x"0014" => if_id_register_next.ir <= x"4823"; -- and R2,R3
+ when x"0016" => if_id_register_next.ir <= x"72b0"; -- jmpz R11
+ when x"0018" => if_id_register_next.ir <= x"a049"; -- ld R4,[R9]
+
+ when x"001A" => if_id_register_next.ir <= x"1841"; -- add R4,#0x1
+ when x"001C" => if_id_register_next.ir <= x"a028"; -- ld R2,[R8]
+ when x"001E" => if_id_register_next.ir <= x"8301"; -- ld R3,#0x1
+ when x"0020" => if_id_register_next.ir <= x"4823"; -- and R2,R3
+
+ when x"0022" => if_id_register_next.ir <= x"72c0"; -- jmpz R12
+
+ when x"0024" => if_id_register_next.ir <= x"8441"; --ld R4,#0x41 (test)
+
+ when x"0028" => if_id_register_next.ir <= x"e049"; -- st R4,[R9]
+
when others => if_id_register_next.ir <= x"0000"; -- nop
end case;
end process;
+
+
end if_state_behavioral;