LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: cvs at opencores.org<cvs@o...>
    Date: Wed Jan 24 23:14:41 CET 2007
    Subject: [cvs-checkins] MODIFIED: rise ...
    Top
    Date: 00/07/01 24:23:14

    Modified: rise/examples uart_sample.s
    Log:
    Removed obsolete line


    Revision Changes Path
    1.2 rise/examples/uart_sample.s

    http://www.opencores.org/cvsweb.shtml/rise/examples/uart_sample.s.diff?r1=1.1&r2=1.2

    (In the diff below, changes in quantity of whitespace are not shown.)

    Index: uart_sample.s
    ===================================================================
    RCS file: /cvsroot/jlechner/rise/examples/uart_sample.s,v
    retrieving revision 1.1
    retrieving revision 1.2
    diff -u -b -r1.1 -r1.2
    --- uart_sample.s 24 Jan 2007 22:13:19 -0000 1.1
    +++ uart_sample.s 24 Jan 2007 22:14:40 -0000 1.2
    @@ -17,8 +17,6 @@
    ld r12, addrlo(check_tdre)
    ldhb r12, addrhi(check_tdre)

    - jmp r12
    -
    /* wait for uart receiver data */
    check_rdrf:
    ld r2, [r8]



     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.