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From: cvs at opencores.org<cvs@o...>
Date: Wed Jan 24 23:03:45 CET 2007
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/07/01 24:23:03

Modified: rise/vhdl dmem.vhd
Log:
Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles

if ordinary memory data or data of an extension module have to be passed on.


Revision Changes Path
1.9 rise/vhdl/dmem.vhd

http://www.opencores.org/cvsweb.shtml/rise/vhdl/dmem.vhd.diff?r1=1.8&r2=1.9

(In the diff below, changes in quantity of whitespace are not shown.)

Index: dmem.vhd
===================================================================
RCS file: /cvsroot/jlechner/rise/vhdl/dmem.vhd,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -b -r1.8 -r1.9
--- dmem.vhd 24 Jan 2007 15:34:57 -0000 1.8
+++ dmem.vhd 24 Jan 2007 22:03:45 -0000 1.9
@@ -76,6 +76,9 @@
signal mem_data_out :MEM_DATA_T;
signal mem_wr_enable: std_logic;

+ signal last_address_int : MEM_ADDR_T;
+ signal last_address_next : MEM_ADDR_T;
+
signal rdy_cnt_sig : IEEE.NUMERIC_STD.unsigned(1 downto 0);
begin -- dmem_rtl

@@ -114,34 +117,60 @@
we => mem_wr_enable);


-uart_txd <= uart_txd_sig;
-uart_rxd_sig <= uart_rxd;
+ uart_txd <= uart_txd_sig;
+ uart_rxd_sig <= uart_rxd;
+
+ store_address: process (clk, reset)
+ begin -- process data_out
+ if reset='0' then
+ last_address_int <= (others => '0');
+ elsif clk'event and clk='1' then
+ last_address_int <= last_address_next;
+ end if;
+ end process store_address;
+
+ process (last_address_int, mem_data_out, uart_rd_data)
+ begin
+ if last_address_int = CONST_UART_STATUS_ADDRESS
+ or last_address_int = CONST_UART_DATA_ADDRESS then
+ data_out <= uart_rd_data;
+ else
+ data_out <= mem_data_out;
+ end if;
+ end process;
+
+ process (wr_enable, addr, data_in, uart_rd_data, mem_data_out)
+ begin

-process (wr_enable, addr, data_in, uart_rd_data, mem_data_out)
-begin
+ mem_addr <= (others => '0');
+ mem_data_in <= (others => '0');
+ mem_wr_enable <= '0';

+ uart_wr <= '0';
+ uart_wr_data <= (others => '0');
+ uart_rd <= '0';

+ last_address_next <= addr;

--- accessing extension modules
-if addr = CONST_UART_STATUS_ADDRESS
+ if addr = CONST_UART_STATUS_ADDRESS
or addr = CONST_UART_DATA_ADDRESS then
+ -- accessing UART
+
uart_address <= addr (1 downto 0);
if wr_enable = '1' then
uart_wr <= '1';
uart_wr_data <= data_in;
else
uart_rd <= '1';
- data_out <= uart_rd_data;
end if;
-else
+ else
-- accessing data memory
mem_addr <= addr(11 downto 0);
- data_out <= mem_data_out;
mem_data_in <= data_in;
mem_wr_enable <= wr_enable;
-end if;
+ end if;

-end process;
+ end process; end dmem_rtl;