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From: cvs at opencores.org<cvs@o...>
Date: Sun Dec 31 23:37:31 CET 2006
Subject: [cvs-checkins] MODIFIED: rise ...
Date: 00/06/12 31:23:37

Modified: rise/vhdl tb_id_stage_unit.vhd
Log:
- added testbench for load immediate and load immediate with high byte.


Revision Changes Path
1.2 rise/vhdl/tb_id_stage_unit.vhd

http://www.opencores.org/cvsweb.shtml/rise/vhdl/tb_id_stage_unit.vhd.diff?r1=1.1&r2=1.2

(In the diff below, changes in quantity of whitespace are not shown.)

Index: tb_id_stage_unit.vhd
===================================================================
RCS file: /cvsroot/cwalter/rise/vhdl/tb_id_stage_unit.vhd,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -b -r1.1 -r1.2
--- tb_id_stage_unit.vhd 13 Dec 2006 02:07:44 -0000 1.1
+++ tb_id_stage_unit.vhd 31 Dec 2006 22:37:30 -0000 1.2
@@ -53,10 +53,10 @@

signal stall_in : std_logic := '0';
signal clear_in : std_logic := '0';
- signal rx : REGISTER_T := (others => '0');
- signal ry : REGISTER_T := (others => '0');
- signal rz : REGISTER_T := (others => '0');
- signal sr : SR_REGISTER_T := (others => '0');
+ signal rx : REGISTER_T;
+ signal ry : REGISTER_T;
+ signal rz : REGISTER_T;
+ signal sr : SR_REGISTER_T;
signal lock_register : LOCK_REGISTER_T;
--Outputs
signal id_ex_register : ID_EX_REGISTER_T;
@@ -67,6 +67,14 @@
signal lock_reg_addr : std_logic_vector(REGISTER_ADDR_WIDTH - 1 downto 0);
signal stall_out : std_logic;

+ constant TB_RX_ADDR_TEST_VALUE : REGISTER_ADDR_T := x"1";
+ constant TB_RX_TEST_VALUE : REGISTER_T := x"0001";
+ constant TB_RY_TEST_VALUE : REGISTER_T := x"0002";
+ constant TB_RZ_TEST_VALUE : REGISTER_T := x"0003";
+ constant TB_SR_TEST_VALUE : SR_REGISTER_T := x"A55A";
+ constant TB_PC_TEST_VALUE : SR_REGISTER_T := x"1234";
+
+ constant TB_CLOCK : time := 20 ns;
begin

-- instantiate the Unit Under Test (UUT)
@@ -93,9 +101,9 @@
cg : process
begin
clk <= '0';
- wait for 10 ns;
+ wait for TB_CLOCK/2;
clk <= '1';
- wait for 10 ns;
+ wait for TB_CLOCK/2;
end process;

tb : process
@@ -104,9 +112,34 @@
wait for 100 ns;
reset <= '1';

- -- stimulus
- if_id_register.pc <= x"1234";
- if_id_register.ir <= "100"& "0" & "0001" & x"55";
+ -- test case: basic functionallity
+ if_id_register.pc <= TB_PC_TEST_VALUE;
+ sr <= TB_SR_TEST_VALUE;
+ rx <= TB_RX_TEST_VALUE;
+ ry <= TB_RY_TEST_VALUE;
+ rz <= TB_RZ_TEST_VALUE;
+
+ wait for TB_CLOCK;
+
+ -- test case: OPCODE_LD_IMM
+ if_id_register.ir <= "100"& "0" & TB_RX_ADDR_TEST_VALUE & x"55";
+ wait for TB_CLOCK;
+ assert id_ex_register.opcode = OPCODE_LD_IMM;
+ assert id_ex_register.immediate = x"0055";
+ assert id_ex_register.cond = COND_UNCONDITIONAL;
+ assert rx_addr = TB_RX_ADDR_TEST_VALUE;
+ assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
+ assert id_ex_register.rX = TB_RX_TEST_VALUE;
+
+ -- test case: OPCODE_LD_IMM_HB
+ if_id_register.ir <= "100"& "1" & TB_RX_ADDR_TEST_VALUE & x"55";
+ wait for TB_CLOCK;
+ assert id_ex_register.opcode = OPCODE_LD_IMM_HB;
+ assert id_ex_register.immediate = x"5500";
+ assert id_ex_register.cond = COND_UNCONDITIONAL;
+ assert rx_addr = TB_RX_ADDR_TEST_VALUE;
+ assert id_ex_register.rX_addr = TB_RX_ADDR_TEST_VALUE;
+ assert id_ex_register.rX = TB_RX_TEST_VALUE;

wait; -- will wait forever
end process;