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From: cvs at opencores.org<cvs@o...>
Date: Fri Dec 29 19:08:56 CET 2006
Subject: [cvs-checkins] MODIFIED: ae18 ...
Date: 00/06/12 29:19:08

Modified: ae18/rtl/verilog ae18_core.v
Log:
Minor code clean up




Revision Changes Path
1.4 ae18/rtl/verilog/ae18_core.v

http://www.opencores.org/cvsweb.shtml/ae18/rtl/verilog/ae18_core.v.diff?r1=1.3&r2=1.4

(In the diff below, changes in quantity of whitespace are not shown.)

Index: ae18_core.v
===================================================================
RCS file: /cvsroot/sybreon/ae18/rtl/verilog/ae18_core.v,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -b -r1.3 -r1.4
--- ae18_core.v 29 Dec 2006 17:52:13 -0000 1.3
+++ ae18_core.v 29 Dec 2006 18:08:56 -0000 1.4
@@ -9,7 +9,7 @@
// Status : Beta/Stable

/*
- * $Id: ae18_core.v,v 1.3 2006/12/29 17:52:13 sybreon Exp $
+ * $Id: ae18_core.v,v 1.4 2006/12/29 18:08:56 sybreon Exp $
*
* Copyright (C) 2006 Shawn Tan Ser Ngiap <shawn.tan@a...>
*
@@ -34,11 +34,12 @@
* need to be integrated with the core. This core provides the necessary
* signals to wire up WISHBONE compatible devices to it.
*
- * 2006-12-29
- * Fixed minor bug with BCC and TBL instructions.
+ * HISTORY
+ * $Log: ae18_core.v,v $
+ * Revision 1.4 2006/12/29 18:08:56 sybreon
+ * Minor code clean up
+ *
*
- * 2006-12-27
- * CVS Checkin
*/

module ae18_core (/*AUTOARG*/